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Publications of Author

1. Richard F. Hobson, J. D. Hoskin, R. W. Spilsbury
   Opportunities for System and User Features in a New APL Interpreter. [Citation Graph (0, 0)][DBLP]
   APL, 1989, pp:190-196 [Conf]
   
2. R. Balakrishnan, Richard F. Hobson
   A Greedy Router with Technology Targetable Output. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1999, pp:252-255 [Conf]
   
3. Richard F. Hobson
   Power Reducing Techniques for Clocked CMOS PLAs. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1998, pp:34-38 [Conf]
   
4. Richard F. Hobson, Allan R. Dyck
   A Multiple-Input Single-Phase Clock Flip-Flop Family. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1999, pp:240-241 [Conf]
   
5. Richard F. Hobson
   Structured Machine Design: An Ongoing Experiement. [Citation Graph (0, 0)][DBLP]
   ISCA, 1981, pp:37-56 [Conf]
   
6. Allan R. Dyck, S. Evenson, H. Fu, Richard F. Hobson
   User selectable feature support for an embedded processor. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:9-12 [Conf]
   
7. Richard F. Hobson, Allan R. Dyck, Keith Cheung
   SoC Features for a Multi-Processor WCDMA Base-station Modem. [Citation Graph (0, 0)][DBLP]
   IWSOC, 2004, pp:318-321 [Conf]
   
8. Richard F. Hobson, P. S. Wong
   A parallel embedded-processor architecture for ATM reassembly. [Citation Graph (0, 0)][DBLP]
   IEEE/ACM Trans. Netw., 1999, v:7, n:1, pp:23-37 [Journal]
   
9. Richard F. Hobson
   A Directly Executable Encoding for APL. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Program. Lang. Syst., 1984, v:6, n:3, pp:314-332 [Journal]
   
10. Richard F. Hobson
    A New Single-Ended SRAM Cell With Write-Assist. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:173-181 [Journal]
    
11. 
    Software sympathetic chip set design. [Citation Graph (, )][DBLP]
    
    
12. 
    A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist. [Citation Graph (, )][DBLP]