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Publications of Author

1. Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky
   Petri Net Based Design and Implementation Methodology for Discrete Event Control Systems. [Citation Graph (0, 0)][DBLP]
   ICATPN, 2001, pp:81-100 [Conf]
   
2. Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
   Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. [Citation Graph (0, 0)][DBLP]
   DATE Designers' Forum, 2006, pp:36-41 [Conf]
   
3. Christophe Layer, Hans-Jörg Pfleiderer
   High Performance Associative Coprocessor Architecture for Advanced Database Searching. [Citation Graph (0, 0)][DBLP]
   Databases and Applications, 2004, pp:87-92 [Conf]
   
4. Christophe Layer, Hans-Jörg Pfleiderer
   A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:648-657 [Conf]
   
5. Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer
   A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:938-942 [Conf]
   
6. Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer
   Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:1097-1100 [Conf]
   
7. Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer
   Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. [Citation Graph (0, 0)][DBLP]
   VLSI, 1999, pp:245-256 [Conf]
   
8. G. Nebel, U. Kleine, Hans-Jörg Pfleiderer
   Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-Applications. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:85-88 [Conf]
   
9. Christophe Layer, Hans-Jörg Pfleiderer, Christoph Heer
   A scalable compact architecture for the computation of integer binary logarithms through linear approximation. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:421-424 [Conf]
   
10. Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
    Regular Routing Architecture for a LUT-based MPGA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:257-262 [Conf]
    
11. Jürgen Rauscher, Hans-Jörg Pfleiderer
    Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:496-503 [Conf]
    
12. Markus Tahedl, Hans-Jörg Pfleiderer
    Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:69-78 [Conf]
    
13. Christophe Layer, Hans-Jörg Pfleiderer
    Vertical Sorting Techniques Accelerating Associative Accesses based Information Retrieval Systems. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:411-416 [Conf]
    
14. Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
    3D Chip Stack Technology Using Through-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:512-518 [Journal]
    
15. Egon Hörbst, H. Oechslein, Hans-Jörg Pfleiderer
    VLSI - Auswirkungen auf konventionelle Rechnerstrukturen. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1985, v:8, n:1, pp:7-19 [Journal]
    
16. Markus Buck, Tim Haulick, Hans-Jörg Pfleiderer
    Self-calibrating microphone arrays for speech signal acquisition: A systematic approach. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2006, v:86, n:6, pp:1230-1238 [Journal]
    
17. Francisco-Javier Veredas, Hans-Jörg Pfleiderer
    Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
    
18. Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer
    Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:405-408 [Conf]
    
19. Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
    LUT-based MPGAs for fast turnaround time conversion flow. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
20. 
    Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. [Citation Graph (, )][DBLP]
    
    
21. 
    Configurable Blocks for Multi-precision Multiplication. [Citation Graph (, )][DBLP]
    
    
22. 
    FPGA implementation of a flexible decoder for long LDPC codes. [Citation Graph (, )][DBLP]
    
    
23. 
    EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. [Citation Graph (, )][DBLP]
    
    
24. 
    Numerically controlled oscillators using linear approximation. [Citation Graph (, )][DBLP]
    
    
25. 
    Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases. [Citation Graph (, )][DBLP]