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Parosh Aziz Abdulla :
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Parosh Aziz Abdulla , Aletta Nylén Timed Petri Nets and BQOs. [Citation Graph (0, 0)][DBLP ] ICATPN, 2001, pp:53-70 [Conf ] Parosh Aziz Abdulla , Noomene Ben Henda , Richard Mayr , Sven Sandberg Eager Markov Chains. [Citation Graph (0, 0)][DBLP ] ATVA, 2006, pp:24-38 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson On the Existence of Network Invariants for Verifying Parameterized Systems. [Citation Graph (0, 0)][DBLP ] Correct System Design, 1999, pp:180-197 [Conf ] Parosh Aziz Abdulla , Aurore Annichini , Saddek Bensalem , Ahmed Bouajjani , Peter Habermehl , Yassine Lakhnech Verification of Infinite-State Systems by Combining Abstraction and Reachability Analysis. [Citation Graph (0, 0)][DBLP ] CAV, 1999, pp:146-159 [Conf ] Parosh Aziz Abdulla , Ahmed Bouajjani , Bengt Jonsson On-the-Fly Analysis of Systems with Unbounded, Lossy FIFO Channels. [Citation Graph (0, 0)][DBLP ] CAV, 1998, pp:305-318 [Conf ] Parosh Aziz Abdulla , Ahmed Bouajjani , Bengt Jonsson , Marcus Nilsson Handling Global Conditions in Parameterized System Verification. [Citation Graph (0, 0)][DBLP ] CAV, 1999, pp:134-145 [Conf ] Parosh Aziz Abdulla , S. Purushothaman Iyer , Aletta Nylén Unfoldings of Unbounded Petri Nets. [Citation Graph (0, 0)][DBLP ] CAV, 2000, pp:495-507 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson Invited Tutorial: Verification of Infinite-State and Parameterized Systems. [Citation Graph (0, 0)][DBLP ] CAV, 2000, pp:4- [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Mats Kindahl , Doron Peled A General Approach to Partial Order Reductions in Symbolic Verification (Extended Abstract). [Citation Graph (0, 0)][DBLP ] CAV, 1998, pp:379-390 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Pritha Mahata , Julien d'Orso Regular Tree Model Checking. [Citation Graph (0, 0)][DBLP ] CAV, 2002, pp:555-568 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Marcus Nilsson , Julien d'Orso Algorithmic Improvements in Regular Model Checking. [Citation Graph (0, 0)][DBLP ] CAV, 2003, pp:236-248 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Marcus Nilsson , Julien d'Orso , Mayank Saksena Regular Model Checking for LTL(MSO). [Citation Graph (0, 0)][DBLP ] CAV, 2004, pp:348-360 [Conf ] Parosh Aziz Abdulla , Christel Baier , S. Purushothaman Iyer , Bengt Jonsson Reasoning about Probabilistic Lossy Channel Systems. [Citation Graph (0, 0)][DBLP ] CONCUR, 2000, pp:320-333 [Conf ] Parosh Aziz Abdulla , Karlis Cerans Simulation Is Decidable for One-Counter Nets (Extended Abstract). [Citation Graph (0, 0)][DBLP ] CONCUR, 1998, pp:253-268 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson Channel Representations in Protocol Verification. [Citation Graph (0, 0)][DBLP ] CONCUR, 2001, pp:1-15 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Marcus Nilsson , Mayank Saksena A Survey of Regular Model Checking. [Citation Graph (0, 0)][DBLP ] CONCUR, 2004, pp:35-48 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Marcus Nilsson , Julien d'Orso Regular Model Checking Made Simple and Efficient. [Citation Graph (0, 0)][DBLP ] CONCUR, 2002, pp:116-130 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson , Ahmed Rezine , Mayank Saksena Proving Liveness by Backwards Reachability. [Citation Graph (0, 0)][DBLP ] CONCUR, 2006, pp:95-109 [Conf ] Parosh Aziz Abdulla , Mats Kindahl Decidability of Simulation and Bisimulation between Lossy Channel Systems and Finite State Systems (Extended Abstract). [Citation Graph (0, 0)][DBLP ] CONCUR, 1995, pp:333-347 [Conf ] Parosh Aziz Abdulla , Ahmed Bouajjani , Julien d'Orso Deciding Monotonic Games. [Citation Graph (0, 0)][DBLP ] CSL, 2003, pp:1-14 [Conf ] Parosh Aziz Abdulla , Stefan Arnborg An Equivalence Decision Problem in Systolic Array Verification. [Citation Graph (0, 0)][DBLP ] Specification and Verification of Concurrent Systems, 1988, pp:236-245 [Conf ] Parosh Aziz Abdulla Verification of Parameterized Timed Systems. [Citation Graph (0, 0)][DBLP ] FORMATS, 2005, pp:95-97 [Conf ] Parosh Aziz Abdulla , Johann Deneux , Pritha Mahata , Aletta Nylén Forward Reachability Analysis of Timed Petri Nets. [Citation Graph (0, 0)][DBLP ] FORMATS/FTRTFT, 2004, pp:343-362 [Conf ] Parosh Aziz Abdulla , Mats Kindahl , Doron Peled An Improved Search Strategy for Lossy Channel Systems. [Citation Graph (0, 0)][DBLP ] FORTE, 1997, pp:251-264 [Conf ] Parosh Aziz Abdulla , Alexander Moshe Rabinovich Verification of Probabilistic Systems with Faulty Communication. [Citation Graph (0, 0)][DBLP ] FoSSaCS, 2003, pp:39-53 [Conf ] Parosh Aziz Abdulla , Pritha Mahata , Richard Mayr Decidability of Zenoness, Syntactic Boundedness and Token-Liveness for Dense-Timed Petri Nets. [Citation Graph (0, 0)][DBLP ] FSTTCS, 2004, pp:58-70 [Conf ] Parosh Aziz Abdulla , Luc Boasson , Ahmed Bouajjani Effective Lossy Queue Languages. [Citation Graph (0, 0)][DBLP ] ICALP, 2001, pp:639-651 [Conf ] Parosh Aziz Abdulla , Johann Deneux , Joël Ouaknine , James Worrell Decidability and Complexity Results for Timed Automata via Channel Machines. [Citation Graph (0, 0)][DBLP ] ICALP, 2005, pp:1089-1101 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson Undecidable Verification Problems for Programs with Unreliable Channels. [Citation Graph (0, 0)][DBLP ] ICALP, 1994, pp:316-327 [Conf ] Parosh Aziz Abdulla , Johann Deneux , Gunnar Stålmarck , Herman Ågren , Ove Åkerlund Designing Safe, Reliable Systems Using Scade. [Citation Graph (0, 0)][DBLP ] ISoLA, 2004, pp:115-129 [Conf ] Parosh Aziz Abdulla , Karlis Cerans , Bengt Jonsson , Yih-Kuen Tsay General Decidability Theorems for Infinite-State Systems. [Citation Graph (0, 0)][DBLP ] LICS, 1996, pp:313-321 [Conf ] Parosh Aziz Abdulla , Johann Deneux , Pritha Mahata Multi-Clock Timed Networks. [Citation Graph (0, 0)][DBLP ] LICS, 2004, pp:345-354 [Conf ] Parosh Aziz Abdulla , Noomene Ben Henda , Richard Mayr Verifying Infinite Markov Chains with a Finite Attractor or the Global Coarseness Property. [Citation Graph (0, 0)][DBLP ] LICS, 2005, pp:127-136 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson Verifying Programs with Unreliable Channels [Citation Graph (0, 0)][DBLP ] LICS, 1993, pp:160-170 [Conf ] Parosh Aziz Abdulla , Aletta Nylén Better is Better than Well: On Efficient Verification of Infinite-State Systems. [Citation Graph (0, 0)][DBLP ] LICS, 2000, pp:132-140 [Conf ] Parosh Aziz Abdulla , Noomene Ben Henda , Richard Mayr , Sven Sandberg Limiting Behavior of Markov Chains with Eager Attractors. [Citation Graph (0, 0)][DBLP ] QEST, 2006, pp:253-264 [Conf ] Parosh Aziz Abdulla , Aurore Annichini , Ahmed Bouajjani Symbolic Verification of Lossy Channel Systems: Application to the Bounded Retransmission Protocol. [Citation Graph (0, 0)][DBLP ] TACAS, 1999, pp:208-222 [Conf ] Parosh Aziz Abdulla , Per Bjesse , Niklas Eén Symbolic Reachability Analysis Based on SAT-Solvers. [Citation Graph (0, 0)][DBLP ] TACAS, 2000, pp:411-425 [Conf ] Parosh Aziz Abdulla , Bengt Jonsson Verifying Networks of Timed Processes (Extended Abstract). [Citation Graph (0, 0)][DBLP ] TACAS, 1998, pp:298-312 [Conf ] Parosh Aziz Abdulla , Axel Legay , Julien d'Orso , Ahmed Rezine Simulation-Based Iteration of Tree Transducers. [Citation Graph (0, 0)][DBLP ] TACAS, 2005, pp:30-44 [Conf ] Parosh Aziz Abdulla , Johann Deneux , Lisa Kaati , Marcus Nilsson Minimization of Non-deterministic Automata with Large Alphabets. [Citation Graph (0, 0)][DBLP ] CIAA, 2005, pp:31-42 [Conf ] Parosh Aziz Abdulla , Lisa Kaati , Johanna Högberg Bisimulation Minimization of Tree Automata. [Citation Graph (0, 0)][DBLP ] CIAA, 2006, pp:173-185 [Conf ] Parosh Aziz Abdulla , Aletta Nylén Better Quasi-Ordered Transition Systems [Citation Graph (0, 0)][DBLP ] CoRR, 2004, v:0, n:, pp:- [Journal ] Parosh Aziz Abdulla , Johann Deneux , Pritha Mahata Closed, Open, and Robust Timed Networks. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2005, v:138, n:3, pp:117-151 [Journal ] Parosh Aziz Abdulla Automatic Verification of a Class Systolic Circuits. [Citation Graph (0, 0)][DBLP ] Formal Asp. Comput., 1992, v:4, n:2, pp:149-194 [Journal ] Parosh Aziz Abdulla , Aurore Collomb-Annichini , Ahmed Bouajjani , Bengt Jonsson Using Forward Reachability Analysis for Verification of Lossy Channel Systems. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2004, v:25, n:1, pp:39-65 [Journal ] Parosh Aziz Abdulla , S. Purushothaman Iyer , Aletta Nylén SAT-Solving the Coverability Problem for Petri Nets. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2004, v:24, n:1, pp:25-43 [Journal ] Parosh Aziz Abdulla , Christel Baier , S. Purushothaman Iyer , Bengt Jonsson Simulating perfect channels with probabilistic lossy channels. [Citation Graph (0, 0)][DBLP ] Inf. Comput., 2005, v:197, n:1-2, pp:22-40 [Journal ] Parosh Aziz Abdulla , Nathalie Bertrand , Alexander Moshe Rabinovich , Ph. Schnoebelen Verification of probabilistic systems with faulty communication. [Citation Graph (0, 0)][DBLP ] Inf. Comput., 2005, v:202, n:2, pp:141-165 [Journal ] Parosh Aziz Abdulla , Karlis Cerans , Bengt Jonsson , Yih-Kuen Tsay Algorithmic Analysis of Programs with Well Quasi-ordered Domains. [Citation Graph (0, 0)][DBLP ] Inf. Comput., 2000, v:160, n:1-2, pp:109-127 [Journal ] Parosh Aziz Abdulla , Bengt Jonsson Verifying Programs with Unreliable Channels. [Citation Graph (0, 0)][DBLP ] Inf. Comput., 1996, v:127, n:2, pp:91-101 [Journal ] Parosh Aziz Abdulla , Bengt Jonsson Undecidable Verification Problems for Programs with Unreliable Channels. [Citation Graph (0, 0)][DBLP ] Inf. Comput., 1996, v:130, n:1, pp:71-90 [Journal ] Parosh Aziz Abdulla , Bengt Jonsson Ensuring completeness of symbolic verification methods for infinite-state systems. [Citation Graph (0, 0)][DBLP ] Theor. Comput. Sci., 2001, v:256, n:1-2, pp:145-167 [Journal ] Parosh Aziz Abdulla , Bengt Jonsson Model checking of systems with many identical timed processes. [Citation Graph (0, 0)][DBLP ] Theor. Comput. Sci., 2003, v:290, n:1, pp:241-264 [Journal ] Parosh Aziz Abdulla , Giorgio Delzanno , Ahmed Rezine Parameterized Verification of Infinite-State Processes with Global Conditions. [Citation Graph (0, 0)][DBLP ] CAV, 2007, pp:145-157 [Conf ] Parosh Aziz Abdulla , Giorgio Delzanno , Laurent Van Begin Comparing the Expressive Power of Well-Structured Transition Systems. [Citation Graph (0, 0)][DBLP ] CSL, 2007, pp:99-114 [Conf ] Parosh Aziz Abdulla , Pavel Krcál , Wang Yi Sampled Universality of Timed Automata. [Citation Graph (0, 0)][DBLP ] FoSSaCS, 2007, pp:2-16 [Conf ] Parosh Aziz Abdulla , Giorgio Delzanno , Noomene Ben Henda , Ahmed Rezine Regular Model Checking Without Transducers (On Efficient Verification of Parameterized Systems). [Citation Graph (0, 0)][DBLP ] TACAS, 2007, pp:721-736 [Conf ] Parosh Aziz Abdulla , Joël Ouaknine , Karin Quaas , James Worrell Zone-Based Universality Analysis for Single-Clock Timed Automata. [Citation Graph (0, 0)][DBLP ] FSEN, 2007, pp:98-112 [Conf ] Parosh Aziz Abdulla , Noomene Ben Henda , Richard Mayr Decisive Markov Chains [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Parosh Aziz Abdulla , Pritha Mahata , Richard Mayr Dense-Timed Petri Nets: Checking Zenoness, Token liveness<br> and<br><br> Boundedness [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Parosh Aziz Abdulla , Axel Legay , Julien d'Orso , Ahmed Rezine Tree regular model checking: A simulation-based approach. [Citation Graph (0, 0)][DBLP ] J. Log. Algebr. Program., 2006, v:69, n:1-2, pp:93-121 [Journal ] Automated Analysis of Data-Dependent Programs with Dynamic Memory. [Citation Graph (, )][DBLP ] Monotonic Abstraction for Programs with Dynamic Memory Heaps. [Citation Graph (, )][DBLP ] Simulation Subsumption in Ramsey-Based Büchi Automata Universality and Inclusion Testing. [Citation Graph (, )][DBLP ] R-Automata. [Citation Graph (, )][DBLP ] Constrained Monotonic Abstraction: A CEGAR for Parameterized Verification. [Citation Graph (, )][DBLP ] 06081 Abstracts Collection -- Software Verification: Infinite-State Model Checking and Static Program Analysis. [Citation Graph (, )][DBLP ] 06081 Executive Summary -- Software Verification: Infinite-State Model Checking and Static Program Analysis. [Citation Graph (, )][DBLP ] Parameterized Tree Systems. [Citation Graph (, )][DBLP ] Approximated Context-Sensitive Analysis for Parameterized Verification. [Citation Graph (, )][DBLP ] Stochastic Games with Lossy Channels. [Citation Graph (, )][DBLP ] Minimal Cost Reachability/Coverability in Priced Timed Petri Nets. [Citation Graph (, )][DBLP ] Mediating for Reduction (on Minimizing Alternating Büchi Automata). [Citation Graph (, )][DBLP ] Monotonic Abstraction in Action. [Citation Graph (, )][DBLP ] Designing Safe, Reliable Systems using Scade. [Citation Graph (, )][DBLP ] On the Qualitative Analysis of Conformon P Systems. [Citation Graph (, )][DBLP ] Infinite-State Verification: From Transition Systems to Markov Chains. [Citation Graph (, )][DBLP ] Forcing Monotonicity in Parameterized Verification: From Multisets to Words. [Citation Graph (, )][DBLP ] Computing Simulations over Tree Automata. [Citation Graph (, )][DBLP ] When Simulation Meets Antichains. [Citation Graph (, )][DBLP ] Handling Parameterized Systems with Non-atomic Global Conditions. [Citation Graph (, )][DBLP ] Composed Bisimulation for Tree Automata. [Citation Graph (, )][DBLP ] A Language-Based Comparison of Extensions of Petri Nets with and without Whole-Place Operations. [Citation Graph (, )][DBLP ] Automatic Verification of Directory-Based Consistency Protocols. [Citation Graph (, )][DBLP ] Sampled Semantics of Timed Automata [Citation Graph (, )][DBLP ] Monotonic Abstraction in Parameterized Verification. [Citation Graph (, )][DBLP ] Universality of R-automata with Value Copying. [Citation Graph (, )][DBLP ] A Uniform (Bi-)Simulation-Based Framework for Reducing Tree Automata. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.461secs