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Wolfgang Rosenstiel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wolfgang Rosenstiel
    RNL - A Language for Digital Systems Design Based on Nets. [Citation Graph (0, 0)][DBLP]
    Selected Papers from the First and the Second European Workshop on Application and Theory of Petri Nets, 1981, pp:50-55 [Conf]
  2. Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
    Towards a Framework and a Design Methodology for Autonomous SoC. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:101-108 [Conf]
  3. Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
    One language or more?: how can we design an SoC at a system level? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:653-654 [Conf]
  4. Tommy Kuhn, Wolfgang Rosenstiel
    Java based object oriented hardware specification and synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:579-582 [Conf]
  5. C. Schulz-Key, Markus Winterholer, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel
    Object-oriented modeling and synthesis of SystemC specifications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:238-243 [Conf]
  6. Ch. Trautwein, Wolfgang Rosenstiel
    Elektronik-CAD-Anwendung im WWW. [Citation Graph (0, 0)][DBLP]
    CAD, 1998, pp:251-261 [Conf]
  7. Oliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn
    Conflict analysis in multiprocess synthesis for optimized system integration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:15-20 [Conf]
  8. Wolfram Hardt, Wolfgang Rosenstiel
    Speed-up estimation for HW/SW-systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:36-43 [Conf]
  9. Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel
    A prototyping environment for hardware/software codesign in the COBRA project. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:10-16 [Conf]
  10. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Worst-case performance analysis of parallel, communicating software processes. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:37-42 [Conf]
  11. Jörg Wilberg, Raul Camposano, Wolfgang Rosenstiel
    Design flow for hardware/software cosynthesis of a video compression system. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:73-80 [Conf]
  12. Cordula Hansen, Francisco Nascimento, Wolfgang Rosenstiel
    An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:678-683 [Conf]
  13. Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai
    A Framework for Object Oriented Hardware Specification, Verification, and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:413-418 [Conf]
  14. Tommy Kuhn, Wolfgang Rosenstiel, Udo Kebschull
    Description and Simulation of Hardware/Software Systems with Java. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:790-793 [Conf]
  15. Prakash M. Peranandam, Pradeep K. Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel
    Fast falsification based on symbolic bounded property checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1077-1082 [Conf]
  16. Hans-Joachim Wunderlich, Wolfgang Rosenstiel
    On fault modeling for dynamic MOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:540-546 [Conf]
  17. N. Bannow, K. Haug, Wolfgang Rosenstiel
    Automatic systemC design configuration for a faster evaluation of different partitioning alternatives. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:217-218 [Conf]
  18. Cristina Barna, Wolfgang Rosenstiel
    Object-Oriented Reuse Methodology for VHDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:689-0 [Conf]
  19. Oliver Bringmann, Wolfgang Rosenstiel
    Cross-Level Hierarchical High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:451-456 [Conf]
  20. Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn
    Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:326-332 [Conf]
  21. Joseph Borel, Frank Ghenassia, Jean-Jacques Bronner, Irmtraud Rugen-Herzig, Wolfgang Rosenstiel, Anton Sauer
    A Design Automation Roadmap for Europe Panel discussion. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:510-0 [Conf]
  22. Joseph Borel, G. Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen
    MEDEA+ and ITRS Roadmaps. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:328-329 [Conf]
  23. Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
    C/C++: progress or deadlock in system-level specification. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:136-137 [Conf]
  24. Joachim Gerlach, Wolfgang Rosenstiel
    A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:226-0 [Conf]
  25. Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel
    Verification by Simulation Comparison using Interface Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:436-0 [Conf]
  26. Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel
    A Hardware Platform for VLIW Based Emulation of Digital Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:747- [Conf]
  27. André Hergenhan, Wolfgang Rosenstiel
    Static Timing Analysis of Embedded Software on Advanced Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:552-559 [Conf]
  28. Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel
    Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:248-255 [Conf]
  29. Hans-Georg Martin, Wolfgang Rosenstiel
    A Comparing Study of Technology Mapping for FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:939-940 [Conf]
  30. Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Rosenstiel
    Flexible specification and application of rule-based transformations in an automotive design flow. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:82-87 [Conf]
  31. Annette Reutter, Wolfgang Rosenstiel
    An Efficient Reuse System for Digital Circuit Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:38-43 [Conf]
  32. Wolfgang Rosenstiel
    Formal Verification: A New Standard CAD Tool for the Industrial Design Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:422-0 [Conf]
  33. Wolfgang Rosenstiel
    Next Generation System Level Design Tools. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:488-0 [Conf]
  34. Wolfgang Rosenstiel, Reinaldo A. Bergamaschi, Frank Ghenassia, Thorsten Groetker, Masamichi Kawarabayashi, Marinus C. van Lier, Albrecht Mayer, Mike Meredith, Mark Milligan, Stuart Swan
    Is there a Market for SystemC Tools? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:950- [Conf]
  35. Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang
    Panel Title: Reconfigurable Computing - Different Perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10476-10477 [Conf]
  36. Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller 0003
    The simulation semantics of systemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:64-70 [Conf]
  37. Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel
    Simulation-guided property checking based on a multi-valued AR-automata. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:742-748 [Conf]
  38. Stephen Schmitt, Wolfgang Rosenstiel
    Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:96-101 [Conf]
  39. Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel
    Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:792-797 [Conf]
  40. Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel
    Instruction Set Emulation for Rapid Prototyping of SoCs . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10562-10569 [Conf]
  41. Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji
    SystemC and SystemVerilog: Where do They Fit? Where are They Going? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:122-129 [Conf]
  42. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Communication Analysis for System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:648-655 [Conf]
  43. Alexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel
    Formal performance analysis and simulation of UML/SysML models for ESL design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:242-247 [Conf]
  44. Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel
    Measurement of IP Qualification Costs and Benefits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:996-1001 [Conf]
  45. Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel
    Emulation of a Fast Reactive Embedded System using a Real Time Operating System. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:764-765 [Conf]
  46. Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel
    Modeling and Formal Verification of Production Automation Systems. [Citation Graph (0, 0)][DBLP]
    SoftSpez Final Report, 2004, pp:541-566 [Conf]
  47. Udo Heuser, Wolfgang Rosenstiel
    Automatic Generation of Local Internet Catalogues Using the Hierarchical Radius-based Competitive Learning. [Citation Graph (0, 0)][DBLP]
    ECAI, 2000, pp:306-310 [Conf]
  48. Heinz-Josef Eikerling, Wolfram Hardt, Joachim Gerlach, Wolfgang Rosenstiel
    A Methodology for Rapid Analysis and Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:252-259 [Conf]
  49. Martin Bogdan, Wolfgang Rosenstiel
    Detection of cluster in Self-Organizing Maps for controlling a prostheses using nerve signals. [Citation Graph (0, 0)][DBLP]
    ESANN, 2001, pp:131-136 [Conf]
  50. Martin Bogdan, Michael Schröder 0002, Wolfgang Rosenstiel
    Towards the restoration of hand grasp function of quadriplegic patients based on an artificial neural net controller using peripheral nerve stimulation - an approach. [Citation Graph (0, 0)][DBLP]
    ESANN, 2003, pp:427-438 [Conf]
  51. Michael Bensch, Michael Schröder 0002, Martin Bogdan, Wolfgang Rosenstiel
    Feature selection for high-dimensional industrial data. [Citation Graph (0, 0)][DBLP]
    ESANN, 2005, pp:375-380 [Conf]
  52. Dirk W. Hoffmann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Simulation Meets Verification: Checking Temporal Properties in SystemC. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1435-0 [Conf]
  53. Walter Lange, Wolfgang Rosenstiel
    VHDL Description and High-Level Synthesis of an ATM Layer Circuit. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1519-0 [Conf]
  54. Sven Ganzenmüller, Simon Pinkenburg, Wolfgang Rosenstiel
    SPH2000: A Parallel Object-Oriented Framework for Particle Simulations with SPH. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:1275-1284 [Conf]
  55. Tobias Grundmann, Marcus Ritt, Wolfgang Rosenstiel
    Object-Oriented Message-Passing with TPO++ (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1081-1084 [Conf]
  56. M. Hipp, Wolfgang Rosenstiel
    Parallel Hybrid Particle Simulations Using MPI and OpenMP. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:189-197 [Conf]
  57. J. Wedeck, Wolfgang Rosenstiel
    Compiling C Programs into Threads. [Citation Graph (0, 0)][DBLP]
    EUROSIM, 1994, pp:153-160 [Conf]
  58. Gunter Haug, Wolfgang Rosenstiel
    Reconfigurable Hardware as Shared Resource for Parallel Threads. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:320-321 [Conf]
  59. Karlheinz Weiß, Ronny Kistner, Arno Kunzmann, Wolfgang Rosenstiel
    Analysis of the XC6000 Architecture for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:245-0 [Conf]
  60. E. Schubert, Wolfgang Rosenstiel
    Combined Spectral Techniques for Boolean Matching. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:38-43 [Conf]
  61. Karlheinz Weiß, Ronny Kistner, Arno Kunzmann, Wolfgang Rosenstiel
    Advantages of the XC6000 Architecture for Embedded System Design (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:255- [Conf]
  62. Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel
    Power estimation approach for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:195-202 [Conf]
  63. Karlheinz Weiß, Thorsten Steckstor, Gernot Koch, Wolfgang Rosenstiel
    Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:235-242 [Conf]
  64. Hans-Jürgen Brand, Dietmar Mueller, Wolfgang Rosenstiel
    Specification and Synthesis of Complex Arithmetic Operators for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:78-88 [Conf]
  65. Gunter Haug, Wolfgang Rosenstiel
    Reconfigurable Hardware as Shared Resource in Multipurpose Computers. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:149-158 [Conf]
  66. Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, Urs Kanus, Wolfgang Straßer
    Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:185-190 [Conf]
  67. Björn Steckelbach, Till Bubeck, Ulrich Fößmeier, Michael Kaufmann, Marcus Ritt, Wolfgang Rosenstiel
    Visualization of Parallel Execution Graphs. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 1998, pp:403-412 [Conf]
  68. Kurt Antreich, Franz J. Rammig, Wolfgang Rosenstiel, Detlef Schmid, Klaus Waldschmidt
    DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1997, pp:93-101 [Conf]
  69. Oliver Bringmann, Wolfgang Rosenstiel
    Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1999, pp:146-153 [Conf]
  70. Wolfgang Eppler, Pablo Castro, Wolfgang Rosenstiel
    Entwurf einer integrierten Schaltung zur Beschleunigung von Koordinatentransformationen mit einem Silicon Compiler. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:52-65 [Conf]
  71. Andreas Herkersdorf, Wolfgang Rosenstiel
    Towards a Framework and a Design Methodology for Autonomic Integrated Systems. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2004, pp:610-615 [Conf]
  72. Detlef Schmid, Raul Camposano, Wolfgang Rosenstiel
    Automatischer Entwurf hochintegrierter Schaltungen aus Beschreibungen der Schaltungsfunktion. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1984, pp:391-406 [Conf]
  73. Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
    An Architecture for Runtime Evaluation of SoC Reliability. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2006, pp:177-0 [Conf]
  74. Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus
    A Design Exploration Environment. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:77-80 [Conf]
  75. Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
    Towards a Framework and a Design Methodology for Autonomic SoC. [Citation Graph (0, 0)][DBLP]
    ICAC, 2005, pp:391-392 [Conf]
  76. Thomas Crämer, Josef Göppert, Wolfgang Rosenstiel
    Modeling Psychological Stereotypes in Self-Organizing Maps. [Citation Graph (0, 0)][DBLP]
    ICANN, 1996, pp:905-910 [Conf]
  77. Thomas Hermle, Martin Bogdan, Cornelius Schwarz, Wolfgang Rosenstiel
    ANN-Based System for Sorting Spike Waveforms Employing Refractory Periods. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2005, pp:121-126 [Conf]
  78. Oliver Bringmann, Wolfgang Rosenstiel
    Resource sharing in hierarchical synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:318-325 [Conf]
  79. Joachim Gerlach, Wolfgang Rosenstiel
    A Methodology and Tool for Automated Transformational High-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:545-548 [Conf]
  80. Thomas Navin Lal, Michael Schröder 0002, N. Jeremy Hill, Hubert Preißl, Thilo Hinterberger, Jürgen Mellinger, Martin Bogdan, Wolfgang Rosenstiel, Thomas Hofmann, Niels Birbaumer, Bernhard Schölkopf
    A brain computer interface with online feedback based on magnetoencephalography. [Citation Graph (0, 0)][DBLP]
    ICML, 2005, pp:465-472 [Conf]
  81. Tobias Grundmann, Marcus Ritt, Wolfgang Rosenstiel
    TPO++: An Object-Oriented Message-Passing Library in C++. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:43-50 [Conf]
  82. Till Bubeck, M. Hiller, Wolfgang Küchlin, Wolfgang Rosenstiel
    Distributed Symbolic Computation with DTS. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1995, pp:231-248 [Conf]
  83. Ralf Seepold, Natividad Martínez Madrid, Andreas Vörg, Wolfgang Rosenstiel, Martin Radetzki, P. Neumann, J. Haase
    A Qualification Platform for Design Reuse. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:75-80 [Conf]
  84. Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn
    Controller Estimation for FPGA Target Architectures during High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:56-61 [Conf]
  85. Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt
    Synchronization Detection for Multi-Process Hierarchical Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:105-110 [Conf]
  86. Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel
    Breakpoints and Breakpoint Detection in Source Level Emulation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:26-0 [Conf]
  87. Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel
    Co-Emulation and Debugging of HW/SW-Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:120-125 [Conf]
  88. Tommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai
    Object oriented hardware synthesis and verification. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:189-194 [Conf]
  89. Wolfgang Rosenstiel
    Embedded Java. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:172- [Conf]
  90. Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
    New design paradigms. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:94- [Conf]
  91. Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Coverage Driven Verification applied to Embedded Software. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:159-164 [Conf]
  92. Josef Göppert, Wolfgang Rosenstiel
    Neurons with Continuous Varying Activation in Self-Organizing Maps. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:419-426 [Conf]
  93. Klaus Beschorner, Wolfgang Rosenstiel
    Realisierung einer Client/Server-Anwendung mit CORBA und Java unter Berücksichtigung bestehender C++-Komponenten. [Citation Graph (0, 0)][DBLP]
    Java-Informations-Tage, 1998, pp:224-237 [Conf]
  94. Stephen Schmitt, Wolfgang Rosenstiel
    Der Einsatz von Jini für die Realisierung durchgängiger Steuerungskonzepte in verteilten eingebetteten Systemen. [Citation Graph (0, 0)][DBLP]
    Java-Informations-Tage, 1999, pp:223-232 [Conf]
  95. Elena P. Sapozhnikova, Wolfgang Rosenstiel
    AFC: ART-Based Fuzzy Classifier. [Citation Graph (0, 0)][DBLP]
    KES, 2003, pp:30-36 [Conf]
  96. P. Gutberlet, Heinrich Krämer, Wolfgang Rosenstiel
    CASCH - ein Scheduling-Algorithmus für "High-Level"-Synthese. [Citation Graph (0, 0)][DBLP]
    Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990, pp:143-156 [Conf]
  97. Thomas Navin Lal, Thilo Hinterberger, Guido Widman, Michael Schröder 0002, N. Jeremy Hill, Wolfgang Rosenstiel, Christian Erich Elger, Bernhard Schölkopf, Niels Birbaumer
    Methods Towards Invasive Human Brain Computer Interfaces. [Citation Graph (0, 0)][DBLP]
    NIPS, 2004, pp:- [Conf]
  98. Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel
    A Design Environment for Processor-Like Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:171-176 [Conf]
  99. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Communication Analysis for Network-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:315-320 [Conf]
  100. Jun Qin, Simon Pinkenburg, Wolfgang Rosenstiel
    Parallel Motif Search using ParSeq. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:601-607 [Conf]
  101. Simon Pinkenburg, Wolfgang Rosenstiel
    Parallel I/O in an Object-Oriented Message-Passing Library. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 2004, pp:251-258 [Conf]
  102. Oliver Bringmann, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann
    Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:114-119 [Conf]
  103. T. Buchholz, Gunter Haug, Udo Kebschull, Gernot Koch, Wolfgang Rosenstiel
    Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:70-0 [Conf]
  104. Carsten Nitsch, Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel
    Embedded System Architecture Design Based on Real-Time Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:228-233 [Conf]
  105. Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel
    Performance Analysis of a RTOS by Emulation of an Embedded System. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:146-0 [Conf]
  106. Martin Bogdan, Wolfgang Rosenstiel
    Application of Artificial Neural Networks for Different Engineering Problems. [Citation Graph (0, 0)][DBLP]
    SOFSEM, 1999, pp:277-294 [Conf]
  107. André Hergenhan, Christoph Weiler, Karlheinz Weiß, Wolfgang Rosenstiel
    Value-Added Services in Industrial Automation. [Citation Graph (0, 0)][DBLP]
    Services and Visualization: Towards User-Friendly Design, 1998, pp:75-89 [Conf]
  108. Axel G. Braun, Jan B. Freuer, Joachim Gerlach, Wolfgang Rosenstiel
    Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:55-0 [Conf]
  109. Pradeep K. Nalla, Roland J. Weiss, Prakash M. Peranandam, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Distributed Symbolic Bounded Property Checking. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:135, n:2, pp:47-63 [Journal]
  110. Kurt Antreich, Franz J. Rammig, Wolfgang Rosenstiel, Detlef Schmid, Klaus Waldschmidt
    DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1997, v:12, n:4, pp:220-223 [Journal]
  111. Klaus Beschorner, Wolfgang Rosenstiel, Wilhelm G. Spruth
    Untersuchungen zur effizienten Kommunikation in EJB-Systemen. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 2004, v:18, n:2, pp:68-79 [Journal]
  112. Thomas Wecker, Ramayya Kumar, Wolfgang Rosenstiel, Heinrich Krämer, Michael Neher
    CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1989, v:4, n:1, pp:37-54 [Journal]
  113. Peter Marwedel, Wolfgang Rosenstiel
    Synthese von Register-Transfer-Strukturen aus Verhaltensbeschriebungen. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1992, v:15, n:1, pp:5-22 [Journal]
  114. Wolfgang Rosenstiel
    IP and design reuse. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:4, pp:191-192 [Journal]
  115. Andreas Vörg, Wolfgang Rosenstiel
    Automation of IP qualification and IP exchange. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:4, pp:323-352 [Journal]
  116. Frank Hoehn, Ekkehard Lindner, Hermann A. Mayer, Thomas Hermle, Wolfgang Rosenstiel
    Neural Networks Evaluating NMR Data: An Approach To Visualize Similarities and Relationships of Sol-Gel Derived Inorganic-Organic and Organometallic Hybrid Polymers1. [Citation Graph (0, 0)][DBLP]
    Journal of Chemical Information and Computer Sciences, 2002, v:42, n:1, pp:36-45 [Journal]
  117. L. Ludwig, Elena P. Sapozhnikova, V. P. Lunin, Wolfgang Rosenstiel
    Error Classification and Yield Prediction of Chips in Semiconductor Industry Applications. [Citation Graph (0, 0)][DBLP]
    Neural Computing and Applications, 2000, v:9, n:3, pp:202-210 [Journal]
  118. Josef Göppert, Wolfgang Rosenstiel
    The Continuous Interpolating Self-organizing Map. [Citation Graph (0, 0)][DBLP]
    Neural Processing Letters, 1997, v:5, n:3, pp:185-192 [Journal]
  119. Raul Camposano, Wolfgang Rosenstiel
    Synthesizing circuits from behavioural descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:171-180 [Journal]
  120. Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull
    Breakpoints and breakpoint detection in source-level emulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:209-230 [Journal]
  121. Matthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel
    Timing simulation of interconnected AUTOSAR software-components. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:474-479 [Conf]
  122. J. A. Brenner, Jan van der Veen, Sándor P. Fekete, J. Oliveira Filho, Wolfgang Rosenstiel
    Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  123. Tobias Oppold, Sven Eisenhardt, Wolfgang Rosenstiel
    Optimization of Area and Performance by Processor-Like Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  124. Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
    Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:338-341 [Conf]
  125. Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel
    A Hybrid Approach for System-Level Design Evaluation. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:165-178 [Conf]
  126. Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel
    Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  127. Tobias Oppold, Thomas Schweizer, Julio A. de Oliveira Filho, Sven Eisenhardt, Wolfgang Rosenstiel
    CRC - Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC - Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:157-0 [Journal]

  128. Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. [Citation Graph (, )][DBLP]

  129. Automated synthesis and verification of embedded systems: wishful thinking or reality? [Citation Graph (, )][DBLP]

  130. Probabilistic performance risk analysis at system-level. [Citation Graph (, )][DBLP]

  131. Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation. [Citation Graph (, )][DBLP]

  132. High-performance timing simulation of embedded software. [Citation Graph (, )][DBLP]

  133. The wild west: conquest of complex hardware-dependent software design. [Citation Graph (, )][DBLP]

  134. Verification of Temporal Properties in Automotive Embedded Software. [Citation Graph (, )][DBLP]

  135. Semiformal verification of temporal properties in automotive hardware dependent software. [Citation Graph (, )][DBLP]

  136. White box performance analysis considering static non-preemptive software scheduling. [Citation Graph (, )][DBLP]

  137. Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. [Citation Graph (, )][DBLP]

  138. Towards assertion-based verification of heterogeneous system designs. [Citation Graph (, )][DBLP]

  139. Simulation-based verification of the MOST NetInterface specification revision 3.0. [Citation Graph (, )][DBLP]

  140. Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures. [Citation Graph (, )][DBLP]

  141. Network-on-Chip Architecture Exploration Framework. [Citation Graph (, )][DBLP]

  142. Direct and inverse solution for a stimulus adaptation problem using SVR. [Citation Graph (, )][DBLP]

  143. Reduced design time by load distribution with CAD framework methodology information. [Citation Graph (, )][DBLP]

  144. Debugging of behavioral VHDL specifications by source level emulation. [Citation Graph (, )][DBLP]

  145. Device selection for system partitioning. [Citation Graph (, )][DBLP]

  146. Timing preserving interface transformations for the synthesis of behavioral VHDL. [Citation Graph (, )][DBLP]

  147. A hardware environment for prototyping and partitioning based on multiple FPGAs. [Citation Graph (, )][DBLP]

  148. A method for partitioning UNITY language in hardware and software. [Citation Graph (, )][DBLP]

  149. System synthesis using behavioural descriptions. [Citation Graph (, )][DBLP]

  150. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]

  151. Evaluation of the Learning Classifier System XCS for SoC run-time control. [Citation Graph (, )][DBLP]

  152. Self-Learning Prediction System for Optimisation of Workload Management in a Mainframe Operating System. [Citation Graph (, )][DBLP]

  153. ASIC Design Project Management Supported by Multi Agent Simulation. [Citation Graph (, )][DBLP]

  154. The use of dARTMAP and fuzzy ARTMAP to solve the quality testing task in semiconductor industry. [Citation Graph (, )][DBLP]

  155. Low Energy Voltage Dithering in Dual VDD Circuits. [Citation Graph (, )][DBLP]

  156. Object-Oriented Message-Passing in Heterogeneous Environments. [Citation Graph (, )][DBLP]

  157. Self-Localization in a Low Cost Bluetooth Environment. [Citation Graph (, )][DBLP]

  158. Generic Self-Adaptation to Reduce Design Effort for System-on-Chip. [Citation Graph (, )][DBLP]

  159. Using genetic algorithms for planning of ASIC chip-design project flows. [Citation Graph (, )][DBLP]

  160. SySifoS: SystemC simulator for sensor and communication systems. [Citation Graph (, )][DBLP]

  161. Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. [Citation Graph (, )][DBLP]

  162. Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties. [Citation Graph (, )][DBLP]

  163. Enabling Automated Code Transformation and Variable Tracing. [Citation Graph (, )][DBLP]

  164. Grid Based Fast Falsification For Bounded Property Checking. [Citation Graph (, )][DBLP]

  165. Efficient and Customizable Integration of Temporal Properties. [Citation Graph (, )][DBLP]

  166. Toward seamless top-down of A/MS systems. [Citation Graph (, )][DBLP]

  167. SystemC-Based Communication and Performance Analysis. [Citation Graph (, )][DBLP]

  168. Performance Analysis and Automated C++ Modularization Using Module-Adapters for SystemC. [Citation Graph (, )][DBLP]

  169. A Seamless Simulink Based System Desing Flow for Automotive Applications. [Citation Graph (, )][DBLP]

  170. Using Symbolic Simulation for Bounded Property Checking. [Citation Graph (, )][DBLP]

  171. Case Study: SystemC-Based Design of an Industrial Exposure Control Unit1. [Citation Graph (, )][DBLP]

  172. Organizing and Planning the ASIC Design Process by Means of a Multi-agent System. [Citation Graph (, )][DBLP]

  173. Automatic synthesis of VLSI architectures for arbitrary lifting-based filter banks and transforms. [Citation Graph (, )][DBLP]

  174. BCCI - A Bidirectional Cortical Communication Interface. [Citation Graph (, )][DBLP]

  175. Optimizing Partial Reconfiguration of Multi-context Architectures. [Citation Graph (, )][DBLP]

  176. Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  177. The Last Byte: The HLS tipping point. [Citation Graph (, )][DBLP]

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