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Wolfgang Rosenstiel :
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Wolfgang Rosenstiel RNL - A Language for Digital Systems Design Based on Nets. [Citation Graph (0, 0)][DBLP ] Selected Papers from the First and the Second European Workshop on Application and Theory of Petri Nets, 1981, pp:50-55 [Conf ] Gabriel Lipsa , Andreas Herkersdorf , Wolfgang Rosenstiel , Oliver Bringmann , Walter Stechele Towards a Framework and a Design Methodology for Autonomous SoC. [Citation Graph (0, 0)][DBLP ] ARCS Workshops, 2005, pp:101-108 [Conf ] Masaharu Imai , Gary Smith , Steven Schulz , Karen Bartleson , Daniel Gajski , Wolfgang Rosenstiel , Peter Flake , Hiroto Yasuura One language or more?: how can we design an SoC at a system level? [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2000, pp:653-654 [Conf ] Tommy Kuhn , Wolfgang Rosenstiel Java based object oriented hardware specification and synthesis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2000, pp:579-582 [Conf ] C. Schulz-Key , Markus Winterholer , Thomas Schweizer , Tommy Kuhn , Wolfgang Rosenstiel Object-oriented modeling and synthesis of SystemC specifications. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:238-243 [Conf ] Ch. Trautwein , Wolfgang Rosenstiel Elektronik-CAD-Anwendung im WWW. [Citation Graph (0, 0)][DBLP ] CAD, 1998, pp:251-261 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Axel Siebenborn Conflict analysis in multiprocess synthesis for optimized system integration. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2005, pp:15-20 [Conf ] Wolfram Hardt , Wolfgang Rosenstiel Speed-up estimation for HW/SW-systems. [Citation Graph (0, 0)][DBLP ] CODES, 1996, pp:36-43 [Conf ] Gernot Koch , Udo Kebschull , Wolfgang Rosenstiel A prototyping environment for hardware/software codesign in the COBRA project. [Citation Graph (0, 0)][DBLP ] CODES, 1994, pp:10-16 [Conf ] Axel Siebenborn , Oliver Bringmann , Wolfgang Rosenstiel Worst-case performance analysis of parallel, communicating software processes. [Citation Graph (0, 0)][DBLP ] CODES, 2002, pp:37-42 [Conf ] Jörg Wilberg , Raul Camposano , Wolfgang Rosenstiel Design flow for hardware/software cosynthesis of a video compression system. [Citation Graph (0, 0)][DBLP ] CODES, 1994, pp:73-80 [Conf ] Cordula Hansen , Francisco Nascimento , Wolfgang Rosenstiel An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:678-683 [Conf ] Tommy Kuhn , Tobias Oppold , Markus Winterholer , Wolfgang Rosenstiel , Mark Edwards , Yaron Kashai A Framework for Object Oriented Hardware Specification, Verification, and Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:413-418 [Conf ] Tommy Kuhn , Wolfgang Rosenstiel , Udo Kebschull Description and Simulation of Hardware/Software Systems with Java. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:790-793 [Conf ] Prakash M. Peranandam , Pradeep K. Nalla , Jürgen Ruf , Roland J. Weiss , Thomas Kropf , Wolfgang Rosenstiel Fast falsification based on symbolic bounded property checking. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:1077-1082 [Conf ] Hans-Joachim Wunderlich , Wolfgang Rosenstiel On fault modeling for dynamic MOS circuits. [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:540-546 [Conf ] N. Bannow , K. Haug , Wolfgang Rosenstiel Automatic systemC design configuration for a faster evaluation of different partitioning alternatives. [Citation Graph (0, 0)][DBLP ] DATE Designers' Forum, 2006, pp:217-218 [Conf ] Cristina Barna , Wolfgang Rosenstiel Object-Oriented Reuse Methodology for VHDL. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:689-0 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel Cross-Level Hierarchical High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:451-456 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Carsten Menn Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:326-332 [Conf ] Joseph Borel , Frank Ghenassia , Jean-Jacques Bronner , Irmtraud Rugen-Herzig , Wolfgang Rosenstiel , Anton Sauer A Design Automation Roadmap for Europe Panel discussion. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:510-0 [Conf ] Joseph Borel , G. Matheron , Ahmed Amine Jerraya , S. Resve , M. Rogers , Wolfgang Rosenstiel , Irmtraud Rugen-Herzig , F. Theewen MEDEA+ and ITRS Roadmaps. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:328-329 [Conf ] Daniel Gajski , Eugenio Villar , Wolfgang Rosenstiel , Vassilios Gerousis , D. Barton , J. Plantin , S. E. Ericsson , Patrizia Cavalloro , Gjalt G. de Jong C/C++: progress or deadlock in system-level specification. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:136-137 [Conf ] Joachim Gerlach , Wolfgang Rosenstiel A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:226-0 [Conf ] Cordula Hansen , Arno Kunzmann , Wolfgang Rosenstiel Verification by Simulation Comparison using Interface Synthesis. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:436-0 [Conf ] Gunter Haug , Udo Kebschull , Wolfgang Rosenstiel A Hardware Platform for VLIW Based Emulation of Digital Designs. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:747- [Conf ] André Hergenhan , Wolfgang Rosenstiel Static Timing Analysis of Embedded Software on Advanced Processor Architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:552-559 [Conf ] Djones Lettnin , Axel G. Braun , Martin Bogdan , Joachim Gerlach , Wolfgang Rosenstiel Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:248-255 [Conf ] Hans-Georg Martin , Wolfgang Rosenstiel A Comparing Study of Technology Mapping for FPGA. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:939-940 [Conf ] Jan-Hendrik Oetjens , Joachim Gerlach , Wolfgang Rosenstiel Flexible specification and application of rule-based transformations in an automotive design flow. [Citation Graph (0, 0)][DBLP ] DATE Designers' Forum, 2006, pp:82-87 [Conf ] Annette Reutter , Wolfgang Rosenstiel An Efficient Reuse System for Digital Circuit Design. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:38-43 [Conf ] Wolfgang Rosenstiel Formal Verification: A New Standard CAD Tool for the Industrial Design Flow. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:422-0 [Conf ] Wolfgang Rosenstiel Next Generation System Level Design Tools. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:488-0 [Conf ] Wolfgang Rosenstiel , Reinaldo A. Bergamaschi , Frank Ghenassia , Thorsten Groetker , Masamichi Kawarabayashi , Marinus C. van Lier , Albrecht Mayer , Mike Meredith , Mark Milligan , Stuart Swan Is there a Market for SystemC Tools? [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:950- [Conf ] Wolfgang Rosenstiel , Rudy Lauwereins , Ivo Bolsens , Chris Rowen , Yankin Tanurhan , Kees A. Vissers , S. Wang Panel Title: Reconfigurable Computing - Different Perspectives. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10476-10477 [Conf ] Jürgen Ruf , Dirk W. Hoffmann , Joachim Gerlach , Thomas Kropf , Wolfgang Rosenstiel , Wolfgang Müller 0003 The simulation semantics of systemC. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:64-70 [Conf ] Jürgen Ruf , Dirk W. Hoffmann , Thomas Kropf , Wolfgang Rosenstiel Simulation-guided property checking based on a multi-valued AR-automata. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:742-748 [Conf ] Stephen Schmitt , Wolfgang Rosenstiel Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:96-101 [Conf ] Jürgen Schnerr , Oliver Bringmann , Wolfgang Rosenstiel Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:792-797 [Conf ] Jürgen Schnerr , Gunter Haug , Wolfgang Rosenstiel Instruction Set Emulation for Rapid Prototyping of SoCs . [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10562-10569 [Conf ] Donatella Sciuto , Grant Martin , Wolfgang Rosenstiel , Stuart Swan , Frank Ghenassia , Peter Flake , Johny Srouji SystemC and SystemVerilog: Where do They Fit? Where are They Going? [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:122-129 [Conf ] Axel Siebenborn , Oliver Bringmann , Wolfgang Rosenstiel Communication Analysis for System-On-Chip Design. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:648-655 [Conf ] Alexander Viehl , Timo Schönwald , Oliver Bringmann , Wolfgang Rosenstiel Formal performance analysis and simulation of UML/SysML models for ESL design. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:242-247 [Conf ] Andreas Vörg , Martin Radetzki , Wolfgang Rosenstiel Measurement of IP Qualification Costs and Benefits. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:996-1001 [Conf ] Karlheinz Weiß , Thorsten Steckstor , Wolfgang Rosenstiel Emulation of a Fast Reactive Embedded System using a Real Time Operating System. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:764-765 [Conf ] Jürgen Ruf , Roland J. Weiss , Thomas Kropf , Wolfgang Rosenstiel Modeling and Formal Verification of Production Automation Systems. [Citation Graph (0, 0)][DBLP ] SoftSpez Final Report, 2004, pp:541-566 [Conf ] Udo Heuser , Wolfgang Rosenstiel Automatic Generation of Local Internet Catalogues Using the Hierarchical Radius-based Competitive Learning. [Citation Graph (0, 0)][DBLP ] ECAI, 2000, pp:306-310 [Conf ] Heinz-Josef Eikerling , Wolfram Hardt , Joachim Gerlach , Wolfgang Rosenstiel A Methodology for Rapid Analysis and Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP ] ECBS, 1996, pp:252-259 [Conf ] Martin Bogdan , Wolfgang Rosenstiel Detection of cluster in Self-Organizing Maps for controlling a prostheses using nerve signals. [Citation Graph (0, 0)][DBLP ] ESANN, 2001, pp:131-136 [Conf ] Martin Bogdan , Michael Schröder 0002 , Wolfgang Rosenstiel Towards the restoration of hand grasp function of quadriplegic patients based on an artificial neural net controller using peripheral nerve stimulation - an approach. [Citation Graph (0, 0)][DBLP ] ESANN, 2003, pp:427-438 [Conf ] Michael Bensch , Michael Schröder 0002 , Martin Bogdan , Wolfgang Rosenstiel Feature selection for high-dimensional industrial data. [Citation Graph (0, 0)][DBLP ] ESANN, 2005, pp:375-380 [Conf ] Dirk W. Hoffmann , Jürgen Ruf , Thomas Kropf , Wolfgang Rosenstiel Simulation Meets Verification: Checking Temporal Properties in SystemC. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 2000, pp:1435-0 [Conf ] Walter Lange , Wolfgang Rosenstiel VHDL Description and High-Level Synthesis of an ATM Layer Circuit. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1999, pp:1519-0 [Conf ] Sven Ganzenmüller , Simon Pinkenburg , Wolfgang Rosenstiel SPH2000: A Parallel Object-Oriented Framework for Particle Simulations with SPH. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2005, pp:1275-1284 [Conf ] Tobias Grundmann , Marcus Ritt , Wolfgang Rosenstiel Object-Oriented Message-Passing with TPO++ (Research Note). [Citation Graph (0, 0)][DBLP ] Euro-Par, 2000, pp:1081-1084 [Conf ] M. Hipp , Wolfgang Rosenstiel Parallel Hybrid Particle Simulations Using MPI and OpenMP. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2004, pp:189-197 [Conf ] J. Wedeck , Wolfgang Rosenstiel Compiling C Programs into Threads. [Citation Graph (0, 0)][DBLP ] EUROSIM, 1994, pp:153-160 [Conf ] Gunter Haug , Wolfgang Rosenstiel Reconfigurable Hardware as Shared Resource for Parallel Threads. [Citation Graph (0, 0)][DBLP ] FCCM, 1998, pp:320-321 [Conf ] Karlheinz Weiß , Ronny Kistner , Arno Kunzmann , Wolfgang Rosenstiel Analysis of the XC6000 Architecture for Embedded System Design. [Citation Graph (0, 0)][DBLP ] FCCM, 1998, pp:245-0 [Conf ] E. Schubert , Wolfgang Rosenstiel Combined Spectral Techniques for Boolean Matching. [Citation Graph (0, 0)][DBLP ] FPGA, 1996, pp:38-43 [Conf ] Karlheinz Weiß , Ronny Kistner , Arno Kunzmann , Wolfgang Rosenstiel Advantages of the XC6000 Architecture for Embedded System Design (Abstract). [Citation Graph (0, 0)][DBLP ] FPGA, 1998, pp:255- [Conf ] Karlheinz Weiß , Carsten Oetker , Igor Katchan , Thorsten Steckstor , Wolfgang Rosenstiel Power estimation approach for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 2000, pp:195-202 [Conf ] Karlheinz Weiß , Thorsten Steckstor , Gernot Koch , Wolfgang Rosenstiel Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System. [Citation Graph (0, 0)][DBLP ] FPGA, 1999, pp:235-242 [Conf ] Hans-Jürgen Brand , Dietmar Mueller , Wolfgang Rosenstiel Specification and Synthesis of Complex Arithmetic Operators for FPGAs. [Citation Graph (0, 0)][DBLP ] FPL, 1994, pp:78-88 [Conf ] Gunter Haug , Wolfgang Rosenstiel Reconfigurable Hardware as Shared Resource in Multipurpose Computers. [Citation Graph (0, 0)][DBLP ] FPL, 1998, pp:149-158 [Conf ] Tobias Oppold , Thomas Schweizer , Tommy Kuhn , Wolfgang Rosenstiel , Urs Kanus , Wolfgang Straßer Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:185-190 [Conf ] Björn Steckelbach , Till Bubeck , Ulrich Fößmeier , Michael Kaufmann , Marcus Ritt , Wolfgang Rosenstiel Visualization of Parallel Execution Graphs. [Citation Graph (0, 0)][DBLP ] Graph Drawing, 1998, pp:403-412 [Conf ] Kurt Antreich , Franz J. Rammig , Wolfgang Rosenstiel , Detlef Schmid , Klaus Waldschmidt DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung, 1997, pp:93-101 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung, 1999, pp:146-153 [Conf ] Wolfgang Eppler , Pablo Castro , Wolfgang Rosenstiel Entwurf einer integrierten Schaltung zur Beschleunigung von Koordinatentransformationen mit einem Silicon Compiler. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (2), 1988, pp:52-65 [Conf ] Andreas Herkersdorf , Wolfgang Rosenstiel Towards a Framework and a Design Methodology for Autonomic Integrated Systems. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (2), 2004, pp:610-615 [Conf ] Detlef Schmid , Raul Camposano , Wolfgang Rosenstiel Automatischer Entwurf hochintegrierter Schaltungen aus Beschreibungen der Schaltungsfunktion. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung, 1984, pp:391-406 [Conf ] Andreas Bernauer , Oliver Bringmann , Wolfgang Rosenstiel , Abdelmajid Bouajila , Walter Stechele , Andreas Herkersdorf An Architecture for Runtime Evaluation of SoC Reliability. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (1), 2006, pp:177-0 [Conf ] Jörg Wilberg , A. Kuth , Raul Camposano , Wolfgang Rosenstiel , Heinrich Theodor Vierhaus A Design Exploration Environment. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:77-80 [Conf ] Gabriel Lipsa , Andreas Herkersdorf , Wolfgang Rosenstiel , Oliver Bringmann , Walter Stechele Towards a Framework and a Design Methodology for Autonomic SoC. [Citation Graph (0, 0)][DBLP ] ICAC, 2005, pp:391-392 [Conf ] Thomas Crämer , Josef Göppert , Wolfgang Rosenstiel Modeling Psychological Stereotypes in Self-Organizing Maps. [Citation Graph (0, 0)][DBLP ] ICANN, 1996, pp:905-910 [Conf ] Thomas Hermle , Martin Bogdan , Cornelius Schwarz , Wolfgang Rosenstiel ANN-Based System for Sorting Spike Waveforms Employing Refractory Periods. [Citation Graph (0, 0)][DBLP ] ICANN (1), 2005, pp:121-126 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel Resource sharing in hierarchical synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:318-325 [Conf ] Joachim Gerlach , Wolfgang Rosenstiel A Methodology and Tool for Automated Transformational High-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP ] ICCD, 2000, pp:545-548 [Conf ] Thomas Navin Lal , Michael Schröder 0002 , N. Jeremy Hill , Hubert Preißl , Thilo Hinterberger , Jürgen Mellinger , Martin Bogdan , Wolfgang Rosenstiel , Thomas Hofmann , Niels Birbaumer , Bernhard Schölkopf A brain computer interface with online feedback based on magnetoencephalography. [Citation Graph (0, 0)][DBLP ] ICML, 2005, pp:465-472 [Conf ] Tobias Grundmann , Marcus Ritt , Wolfgang Rosenstiel TPO++: An Object-Oriented Message-Passing Library in C++. [Citation Graph (0, 0)][DBLP ] ICPP, 2000, pp:43-50 [Conf ] Till Bubeck , M. Hiller , Wolfgang Küchlin , Wolfgang Rosenstiel Distributed Symbolic Computation with DTS. [Citation Graph (0, 0)][DBLP ] IRREGULAR, 1995, pp:231-248 [Conf ] Ralf Seepold , Natividad Martínez Madrid , Andreas Vörg , Wolfgang Rosenstiel , Martin Radetzki , P. Neumann , J. Haase A Qualification Platform for Design Reuse. [Citation Graph (0, 0)][DBLP ] ISQED, 2002, pp:75-80 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Carsten Menn Controller Estimation for FPGA Target Architectures during High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] ISSS, 2002, pp:56-61 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Dirk Reichardt Synchronization Detection for Multi-Process Hierarchical Synthesis. [Citation Graph (0, 0)][DBLP ] ISSS, 1998, pp:105-110 [Conf ] Gernot Koch , Udo Kebschull , Wolfgang Rosenstiel Breakpoints and Breakpoint Detection in Source Level Emulation. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:26-0 [Conf ] Gernot Koch , Udo Kebschull , Wolfgang Rosenstiel Co-Emulation and Debugging of HW/SW-Systems. [Citation Graph (0, 0)][DBLP ] ISSS, 1997, pp:120-125 [Conf ] Tommy Kuhn , Tobias Oppold , C. Schulz-Key , Markus Winterholer , Wolfgang Rosenstiel , Mark Edwards , Yaron Kashai Object oriented hardware synthesis and verification. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:189-194 [Conf ] Wolfgang Rosenstiel Embedded Java. [Citation Graph (0, 0)][DBLP ] ISSS, 2000, pp:172- [Conf ] Wolfgang Rosenstiel , Brian Bailey , Masahiro Fujita , Guang R. Gao , Rajesh K. Gupta , Preeti Ranjan Panda New design paradigms. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:94- [Conf ] Djones Lettnin , Markus Winterholer , Axel G. Braun , Joachim Gerlach , Jürgen Ruf , Thomas Kropf , Wolfgang Rosenstiel Coverage Driven Verification applied to Embedded Software. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2007, pp:159-164 [Conf ] Josef Göppert , Wolfgang Rosenstiel Neurons with Continuous Varying Activation in Self-Organizing Maps. [Citation Graph (0, 0)][DBLP ] IWANN, 1995, pp:419-426 [Conf ] Klaus Beschorner , Wolfgang Rosenstiel Realisierung einer Client/Server-Anwendung mit CORBA und Java unter Berücksichtigung bestehender C++-Komponenten. [Citation Graph (0, 0)][DBLP ] Java-Informations-Tage, 1998, pp:224-237 [Conf ] Stephen Schmitt , Wolfgang Rosenstiel Der Einsatz von Jini für die Realisierung durchgängiger Steuerungskonzepte in verteilten eingebetteten Systemen. [Citation Graph (0, 0)][DBLP ] Java-Informations-Tage, 1999, pp:223-232 [Conf ] Elena P. Sapozhnikova , Wolfgang Rosenstiel AFC: ART-Based Fuzzy Classifier. [Citation Graph (0, 0)][DBLP ] KES, 2003, pp:30-36 [Conf ] P. Gutberlet , Heinrich Krämer , Wolfgang Rosenstiel CASCH - ein Scheduling-Algorithmus für "High-Level"-Synthese. [Citation Graph (0, 0)][DBLP ] Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990, pp:143-156 [Conf ] Thomas Navin Lal , Thilo Hinterberger , Guido Widman , Michael Schröder 0002 , N. Jeremy Hill , Wolfgang Rosenstiel , Christian Erich Elger , Bernhard Schölkopf , Niels Birbaumer Methods Towards Invasive Human Brain Computer Interfaces. [Citation Graph (0, 0)][DBLP ] NIPS, 2004, pp:- [Conf ] Tobias Oppold , Thomas Schweizer , Tommy Kuhn , Wolfgang Rosenstiel A Design Environment for Processor-Like Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] PARELEC, 2004, pp:171-176 [Conf ] Axel Siebenborn , Oliver Bringmann , Wolfgang Rosenstiel Communication Analysis for Network-on-Chip Design. [Citation Graph (0, 0)][DBLP ] PARELEC, 2004, pp:315-320 [Conf ] Jun Qin , Simon Pinkenburg , Wolfgang Rosenstiel Parallel Motif Search using ParSeq. [Citation Graph (0, 0)][DBLP ] Parallel and Distributed Computing and Networks, 2005, pp:601-607 [Conf ] Simon Pinkenburg , Wolfgang Rosenstiel Parallel I/O in an Object-Oriented Message-Passing Library. [Citation Graph (0, 0)][DBLP ] PVM/MPI, 2004, pp:251-258 [Conf ] Oliver Bringmann , Wolfgang Rosenstiel , Annette Muth , Georg Färber , Frank Slomka , Richard Hofmann Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 1999, pp:114-119 [Conf ] T. Buchholz , Gunter Haug , Udo Kebschull , Gernot Koch , Wolfgang Rosenstiel Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures. [Citation Graph (0, 0)][DBLP ] International Workshop on Rapid System Prototyping, 1998, pp:70-0 [Conf ] Carsten Nitsch , Karlheinz Weiß , Thorsten Steckstor , Wolfgang Rosenstiel Embedded System Architecture Design Based on Real-Time Emulation. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2000, pp:228-233 [Conf ] Karlheinz Weiß , Thorsten Steckstor , Wolfgang Rosenstiel Performance Analysis of a RTOS by Emulation of an Embedded System. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 1999, pp:146-0 [Conf ] Martin Bogdan , Wolfgang Rosenstiel Application of Artificial Neural Networks for Different Engineering Problems. [Citation Graph (0, 0)][DBLP ] SOFSEM, 1999, pp:277-294 [Conf ] André Hergenhan , Christoph Weiler , Karlheinz Weiß , Wolfgang Rosenstiel Value-Added Services in Industrial Automation. [Citation Graph (0, 0)][DBLP ] Services and Visualization: Towards User-Friendly Design, 1998, pp:75-89 [Conf ] Axel G. Braun , Jan B. Freuer , Joachim Gerlach , Wolfgang Rosenstiel Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:55-0 [Conf ] Pradeep K. Nalla , Roland J. Weiss , Prakash M. Peranandam , Jürgen Ruf , Thomas Kropf , Wolfgang Rosenstiel Distributed Symbolic Bounded Property Checking. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2006, v:135, n:2, pp:47-63 [Journal ] Kurt Antreich , Franz J. Rammig , Wolfgang Rosenstiel , Detlef Schmid , Klaus Waldschmidt DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme. [Citation Graph (0, 0)][DBLP ] Inform., Forsch. Entwickl., 1997, v:12, n:4, pp:220-223 [Journal ] Klaus Beschorner , Wolfgang Rosenstiel , Wilhelm G. Spruth Untersuchungen zur effizienten Kommunikation in EJB-Systemen. [Citation Graph (0, 0)][DBLP ] Inform., Forsch. Entwickl., 2004, v:18, n:2, pp:68-79 [Journal ] Thomas Wecker , Ramayya Kumar , Wolfgang Rosenstiel , Heinrich Krämer , Michael Neher CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. [Citation Graph (0, 0)][DBLP ] Inform., Forsch. Entwickl., 1989, v:4, n:1, pp:37-54 [Journal ] Peter Marwedel , Wolfgang Rosenstiel Synthese von Register-Transfer-Strukturen aus Verhaltensbeschriebungen. [Citation Graph (0, 0)][DBLP ] Informatik Spektrum, 1992, v:15, n:1, pp:5-22 [Journal ] Wolfgang Rosenstiel IP and design reuse. [Citation Graph (0, 0)][DBLP ] Integration, 2004, v:37, n:4, pp:191-192 [Journal ] Andreas Vörg , Wolfgang Rosenstiel Automation of IP qualification and IP exchange. [Citation Graph (0, 0)][DBLP ] Integration, 2004, v:37, n:4, pp:323-352 [Journal ] Frank Hoehn , Ekkehard Lindner , Hermann A. Mayer , Thomas Hermle , Wolfgang Rosenstiel Neural Networks Evaluating NMR Data: An Approach To Visualize Similarities and Relationships of Sol-Gel Derived Inorganic-Organic and Organometallic Hybrid Polymers1. [Citation Graph (0, 0)][DBLP ] Journal of Chemical Information and Computer Sciences, 2002, v:42, n:1, pp:36-45 [Journal ] L. Ludwig , Elena P. Sapozhnikova , V. P. Lunin , Wolfgang Rosenstiel Error Classification and Yield Prediction of Chips in Semiconductor Industry Applications. [Citation Graph (0, 0)][DBLP ] Neural Computing and Applications, 2000, v:9, n:3, pp:202-210 [Journal ] Josef Göppert , Wolfgang Rosenstiel The Continuous Interpolating Self-organizing Map. [Citation Graph (0, 0)][DBLP ] Neural Processing Letters, 1997, v:5, n:3, pp:185-192 [Journal ] Raul Camposano , Wolfgang Rosenstiel Synthesizing circuits from behavioural descriptions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:171-180 [Journal ] Gernot Koch , Wolfgang Rosenstiel , Udo Kebschull Breakpoints and breakpoint detection in source-level emulation. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:209-230 [Journal ] Matthias Krause , Oliver Bringmann , André Hergenhan , Gökhan Tabanoglu , Wolfgang Rosenstiel Timing simulation of interconnected AUTOSAR software-components. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:474-479 [Conf ] J. A. Brenner , Jan van der Veen , Sándor P. Fekete , J. Oliveira Filho , Wolfgang Rosenstiel Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] FPL, 2006, pp:1-6 [Conf ] Tobias Oppold , Sven Eisenhardt , Wolfgang Rosenstiel Optimization of Area and Performance by Processor-Like Reconfiguration. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-8 [Conf ] Abdelmajid Bouajila , Johannes Zeppenfeld , Walter Stechele , Andreas Herkersdorf , Andreas Bernauer , Oliver Bringmann , Wolfgang Rosenstiel Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP ] VLSI-SoC, 2006, pp:338-341 [Conf ] Alexander Viehl , Markus Schwarz , Oliver Bringmann , Wolfgang Rosenstiel A Hybrid Approach for System-Level Design Evaluation. [Citation Graph (0, 0)][DBLP ] IESS, 2007, pp:165-178 [Conf ] Jürgen Schnerr , Oliver Bringmann , Wolfgang Rosenstiel Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Tobias Oppold , Thomas Schweizer , Julio A. de Oliveira Filho , Sven Eisenhardt , Wolfgang Rosenstiel CRC - Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC - Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen). [Citation Graph (0, 0)][DBLP ] it - Information Technology, 2007, v:49, n:3, pp:157-0 [Journal ] Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. 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[Citation Graph (, )][DBLP ] Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP ] The Last Byte: The HLS tipping point. [Citation Graph (, )][DBLP ] Search in 0.022secs, Finished in 0.932secs