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Giuseppe Ascia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Giuseppe Ascia, Vincenzo Catania
    An Optimized Parallel RISC Processor for Fuzzy Computing. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:454-456 [Conf]
  2. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    Exploring Design Space of VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:86-91 [Conf]
  3. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:245-250 [Conf]
  4. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:940-943 [Conf]
  5. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Parameterised system design based on genetic algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:177-182 [Conf]
  6. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Multi-objective mapping for mesh-based NoC architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:182-187 [Conf]
  7. Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
    Fuzzy decision making in embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:223-228 [Conf]
  8. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    Multi-objective Optimization of a Parameterized VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:191-198 [Conf]
  9. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:65-72 [Conf]
  10. Giuseppe Ascia, Vincenzo Catania
    A General Purpose Processor Oriented Fuzzy Reasoning. [Citation Graph (0, 0)][DBLP]
    FUZZ-IEEE, 2001, pp:352-355 [Conf]
  11. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:157-168 [Conf]
  12. Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno
    A Fuzzy Buffer Management Scheme For ATM and IP Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2001, pp:1539-1547 [Conf]
  13. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An efficient buffer management policy based on an integrated Fuzzy-GA approach. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2002, pp:- [Conf]
  14. Giuseppe Ascia, Giuseppe Ficili, Daniela Panno
    Design of a VLSI fuzzy processor for ATM traffic sources management. [Citation Graph (0, 0)][DBLP]
    LCN, 1995, pp:62-0 [Conf]
  15. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:21-30 [Conf]
  16. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An adaptive fuzzy threshold scheme for high performance shared-memory switches. [Citation Graph (0, 0)][DBLP]
    SAC, 2001, pp:456-461 [Conf]
  17. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Approach To Bus Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:426-431 [Conf]
  18. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:245-250 [Conf]
  19. Giuseppe Ascia, Vincenzo Catania
    Design of a VLSI parallel processor for fuzzy computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:315-320 [Conf]
  20. Giuseppe Ascia, Vincenzo Catania
    A Framework for a Parallel Architecture Dedicated to Soft Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:318-321 [Conf]
  21. Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili
    Design of a VLSI Hardware PET Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:253-256 [Conf]
  22. Vincenzo Catania, Giuseppe Ascia
    A VLSI Parallel Architecture for Fuzzy Expert Systems. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:421-447 [Journal]
  23. Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    A Reconfigurable Parallel Architecture for a Fuzzy Processor. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1996, v:88, n:1-4, pp:299-315 [Journal]
  24. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:4, pp:370-394 [Journal]
  25. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An efficient fuzzy system for traffic management in high-speed packet-switched networks. [Citation Graph (0, 0)][DBLP]
    Soft Comput., 2001, v:5, n:4, pp:247-256 [Journal]
  26. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:635-645 [Journal]
  27. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A GA-based design space exploration framework for parameterized system-on-a-chip platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2004, v:8, n:4, pp:329-346 [Journal]
  28. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An evolutionary management scheme in high-performance packet switches. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2005, v:13, n:2, pp:262-275 [Journal]
  29. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:115-122 [Conf]
  30. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An evolutionary approach to network-on-chip mapping problem. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:112-119 [Conf]
  31. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
    An evolutionary approach for reducing the energy in address buses. [Citation Graph (0, 0)][DBLP]
    ISICT, 2003, pp:76-81 [Conf]
  32. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    Efficient design space exploration for application specific systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:733-750 [Journal]

  33. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. [Citation Graph (, )][DBLP]


  34. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. [Citation Graph (, )][DBLP]


  35. Hyperblock formation: a power/energy perspective for high performance VLIW architectures. [Citation Graph (, )][DBLP]


  36. An evolutionary approach for reducing the switching activity in address buses. [Citation Graph (, )][DBLP]


  37. Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. [Citation Graph (, )][DBLP]


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