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Vincenzo Catania: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita
    Design and Performance Analysis of a Disk Array System. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:10, pp:1236-1247 [Journal]
  2. Giuseppe Ascia, Vincenzo Catania
    An Optimized Parallel RISC Processor for Fuzzy Computing. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:454-456 [Conf]
  3. Vincenzo Catania, Giuseppe Ficili, Daniela Panno
    A Framework for Traffic Control in Integrated Services Networks Based on Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:427-429 [Conf]
  4. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    Exploring Design Space of VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:86-91 [Conf]
  5. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:245-250 [Conf]
  6. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:940-943 [Conf]
  7. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Parameterised system design based on genetic algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:177-182 [Conf]
  8. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Multi-objective mapping for mesh-based NoC architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:182-187 [Conf]
  9. Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
    A methodology for design of application specific deadlock-free routing algorithms for NoC systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:142-147 [Conf]
  10. Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
    Fuzzy decision making in embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:223-228 [Conf]
  11. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    Multi-objective Optimization of a Parameterized VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:191-198 [Conf]
  12. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:65-72 [Conf]
  13. Giuseppe Ascia, Vincenzo Catania
    A General Purpose Processor Oriented Fuzzy Reasoning. [Citation Graph (0, 0)][DBLP]
    FUZZ-IEEE, 2001, pp:352-355 [Conf]
  14. Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo
    A soft computing approach to hardware software codesign. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:158-163 [Conf]
  15. Vincenzo Catania, O. Granato, Antonio Puliafito, Lorenzo Vita
    PMT: A Tool to Monitor Performances in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    HPDC, 1994, pp:279-286 [Conf]
  16. Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita
    Performance Evaluation of a Partial Dynamic Declustering Disk Array System. [Citation Graph (0, 0)][DBLP]
    HPDC, 1994, pp:244-252 [Conf]
  17. Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono
    Evolving Fuzzy C-Means: An intelligent technique for efficient diagnosis of children mental retardation level from databases with missing values. [Citation Graph (0, 0)][DBLP]
    IC-AI, 2006, pp:290-296 [Conf]
  18. Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno
    A fuzzy decision maker for source traffic control in high speed networks. [Citation Graph (0, 0)][DBLP]
    ICNP, 1995, pp:136-143 [Conf]
  19. Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo
    A Framework for Codesign Based on Fuzzy Logic and Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 1995, pp:797-804 [Conf]
  20. Salvatore Casale, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    A Multiple Spanning Tree Protocol in Bridged LANs. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:633-638 [Conf]
  21. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:157-168 [Conf]
  22. Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno
    A Fuzzy Buffer Management Scheme For ATM and IP Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2001, pp:1539-1547 [Conf]
  23. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An efficient buffer management policy based on an integrated Fuzzy-GA approach. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2002, pp:- [Conf]
  24. Vincenzo Catania, Mario Gerla, Claudio Pavanelli
    A Routing Strategy for MAN Interconnection. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1991, pp:608-615 [Conf]
  25. Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    Availability and Performability Assessment in LAN Interconnection. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1990, pp:1181-1187 [Conf]
  26. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:21-30 [Conf]
  27. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An adaptive fuzzy threshold scheme for high performance shared-memory switches. [Citation Graph (0, 0)][DBLP]
    SAC, 2001, pp:456-461 [Conf]
  28. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Approach To Bus Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:426-431 [Conf]
  29. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:245-250 [Conf]
  30. Giuseppe Ascia, Vincenzo Catania
    Design of a VLSI parallel processor for fuzzy computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:315-320 [Conf]
  31. Giuseppe Ascia, Vincenzo Catania
    A Framework for a Parallel Architecture Dedicated to Soft Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:318-321 [Conf]
  32. Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili
    Design of a VLSI Hardware PET Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:253-256 [Conf]
  33. Vincenzo Catania, Marco Russo
    Analog gates for a VLSI fuzzy processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:299-304 [Conf]
  34. Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    A Model for Performance Evaluation of Gracefully Degrading Systems. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1993, v:36, n:2, pp:177-185 [Journal]
  35. Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita
    Monitoring performance in distributed systems. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1996, v:19, n:9-10, pp:788-803 [Journal]
  36. Vincenzo Catania, Giuseppe Ficili, Daniela Panno
    On the impact of traffic control algorithms on resource management in ATM networks. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1999, v:22, n:3, pp:258-265 [Journal]
  37. Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    High-speed data service in distributed systems based on SMDS. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1993, v:16, n:7, pp:394-402 [Journal]
  38. Salvatore Casale, Vincenzo Catania, Aurelio La Corte
    Service integration issues on an ATM DQDB MAN. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1994, v:17, n:6, pp:407-418 [Journal]
  39. Salvatore Casale, Vincenzo Catania, Aurelio La Corte, Lorenzo Vita
    Service management on an ATM DQDB MAN. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1993, v:16, n:3, pp:147-154 [Journal]
  40. Salvatore Casale, Vincenzo Catania, Alberto Faro, Nikolai Parchenkov, Lorenzo Vita
    Design and performance evaluation of an optical fibre LAN with double token rings. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1989, v:12, n:3, pp:158-166 [Journal]
  41. Vincenzo Catania, Salvatore Cavalieri, Lorenzo Vita
    Rearrangeable switch fabric for fast packet switching. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1991, v:14, n:8, pp:451-460 [Journal]
  42. Vincenzo Catania, Giuseppe Ascia
    A VLSI Parallel Architecture for Fuzzy Expert Systems. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:421-447 [Journal]
  43. Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    A Reconfigurable Parallel Architecture for a Fuzzy Processor. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1996, v:88, n:1-4, pp:299-315 [Journal]
  44. Vincenzo Catania, Giuseppe Ficili, Daniela Panno
    An integrated framework for traffic control in ATM networks based on soft-computing techniques. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2001, v:138, n:1-4, pp:31-44 [Journal]
  45. Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
    A Fuzzy Approach to Mapping Problems. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1996, v:95, n:3, pp:191-217 [Journal]
  46. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:4, pp:370-394 [Journal]
  47. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An efficient fuzzy system for traffic management in high-speed packet-switched networks. [Citation Graph (0, 0)][DBLP]
    Soft Comput., 2001, v:5, n:4, pp:247-256 [Journal]
  48. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:635-645 [Journal]
  49. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A GA-based design space exploration framework for parameterized system-on-a-chip platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2004, v:8, n:4, pp:329-346 [Journal]
  50. Giuseppe Ascia, Vincenzo Catania, Daniela Panno
    An evolutionary management scheme in high-performance packet switches. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2005, v:13, n:2, pp:262-275 [Journal]
  51. Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno
    A comparative analysis of fuzzy versus conventional policing mechanisms for ATM networks. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 1996, v:4, n:3, pp:449-459 [Journal]
  52. Alessandro G. Di Nuovo, Vincenzo Catania
    On External Measures for Validation of Fuzzy Partitions. [Citation Graph (0, 0)][DBLP]
    IFSA, 2007, pp:491-501 [Conf]
  53. Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania
    Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  54. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:115-122 [Conf]
  55. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An evolutionary approach to network-on-chip mapping problem. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:112-119 [Conf]
  56. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
    An evolutionary approach for reducing the energy in address buses. [Citation Graph (0, 0)][DBLP]
    ISICT, 2003, pp:76-81 [Conf]
  57. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    Efficient design space exploration for application specific systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:733-750 [Journal]

  58. High Performance Computing for Embedded System Design: A Case Study. [Citation Graph (, )][DBLP]


  59. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. [Citation Graph (, )][DBLP]


  60. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. [Citation Graph (, )][DBLP]


  61. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. [Citation Graph (, )][DBLP]


  62. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. [Citation Graph (, )][DBLP]


  63. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. [Citation Graph (, )][DBLP]


  64. Performance analysis of DQDB behaviour with priority levels. [Citation Graph (, )][DBLP]


  65. Hyperblock formation: a power/energy perspective for high performance VLIW architectures. [Citation Graph (, )][DBLP]


  66. Linguistic Modifiers to Improve the Accuracy-Interpretability Trade-Off in Multi-Objective Genetic Design of Fuzzy Rule Based Classifier Systems. [Citation Graph (, )][DBLP]


  67. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. [Citation Graph (, )][DBLP]


  68. An evolutionary approach for reducing the switching activity in address buses. [Citation Graph (, )][DBLP]


  69. Psychology with soft computing: An integrated approach and its applications. [Citation Graph (, )][DBLP]


  70. Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. [Citation Graph (, )][DBLP]


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