The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Rolf Drechsler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rolf Drechsler, Nicole Drechsler
    Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 2003, pp:109-114 [Conf]
  2. Raik Brinkmann, Rolf Drechsler
    RTL-Datapath Verification using Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:741-746 [Conf]
  3. Rolf Drechsler, Bernd Becker
    Learning heuristics by genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Rolf Drechsler, Nicole Drechsler
    Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:303-0 [Conf]
  5. Rolf Drechsler, Stefan Höreth
    Manipulation of *BMDs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:433-438 [Conf]
  6. Rüdiger Ebendt, Rolf Drechsler
    Lower bounds for dynamic BDD reordering. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:579-582 [Conf]
  7. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Minimization of the expected path length in BDDs based on local changes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:865-870 [Conf]
  8. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combining ordered best-first search with branch and bound for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:875-878 [Conf]
  9. Görschwin Fey, Rolf Drechsler
    Improving simulation-based verification by means of formal methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:640-643 [Conf]
  10. Wolfgang Günther, Rolf Drechsler
    Minimization of Free BDDs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:323-326 [Conf]
  11. Gueesang Lee, Rolf Drechsler
    ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:75-80 [Conf]
  12. Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler
    Low power optimization technique for BDD mapped circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:615-621 [Conf]
  13. Junhao Shi, Görschwin Fey, Rolf Drechsler
    Bridging fault testability of BDD circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:188-191 [Conf]
  14. Yibin Ye, Kaushik Roy, Rolf Drechsler
    Power Consumption in XOR-Based Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:299-302 [Conf]
  15. Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer
    AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:148-0 [Conf]
  16. Junhao Shi, Görschwin Fey, Rolf Drechsler
    BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:290-293 [Conf]
  17. Daniel Große, Rolf Drechsler
    Acceleration of SAT-Based Iterative Property Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:349-353 [Conf]
  18. Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
    Fast Exact Minimization of BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:200-205 [Conf]
  19. Rolf Drechsler, Wolfgang Günther
    Using Lower Bounds During Dynamic BDD Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:29-32 [Conf]
  20. Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
    Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:415-419 [Conf]
  21. Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
    Efficient minimization of fully testable 2-SPP networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1300-1305 [Conf]
  22. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combination of Lower Bounds in Exact BDD Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10758-10763 [Conf]
  23. Görschwin Fey, Daniel Große, Rolf Drechsler
    Avoiding false negatives in formal verification for protocol-driven blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1225-1226 [Conf]
  24. Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    On the relation between simulation-based and SAT-based diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1139-1144 [Conf]
  25. Stefan Höreth, Rolf Drechsler
    Dynamic Minimization of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:612-617 [Conf]
  26. Stefan Höreth, Rolf Drechsler
    Formal Verification of Word-Level Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:52-57 [Conf]
  27. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee
    Managing Don't Cares in Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:260-265 [Conf]
  28. Mitchell A. Thornton, Rolf Drechsler
    Spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:713-719 [Conf]
  29. Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler
    Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:758-759 [Conf]
  30. Daniel Tille, Görschwin Fey, Rolf Drechsler
    Instance Generation for SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:153-156 [Conf]
  31. Rolf Drechsler, Daniel Große
    Reachability Analysis for Formal Verification of SystemC. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:337-340 [Conf]
  32. Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
    Level Assignment for Displaying Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:148-151 [Conf]
  33. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
    Recursive Bi-Partitioning of Netlists for Large Number of Partitions. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:38-44 [Conf]
  34. Görschwin Fey, Junhao Shi, Rolf Drechsler
    BDD Circuit Optimization for Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:168-172 [Conf]
  35. Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
    Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:54-61 [Conf]
  36. Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
    Fast Heuristics for the Edge Coloring of Large Graphs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:230-239 [Conf]
  37. Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
    Decision Diagram Optimization Using Copy Properties. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:236-243 [Conf]
  38. Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler
    Minimization of OPKFDDs Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:72-78 [Conf]
  39. Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Multi-objective Optimisation Based on Relation Favour. [Citation Graph (0, 0)][DBLP]
    EMO, 2001, pp:154-166 [Conf]
  40. André Sülflow, Nicole Drechsler, Rolf Drechsler
    Robust Multi-Objective Optimization in High Dimensional Spaces. [Citation Graph (0, 0)][DBLP]
    EMO, 2006, pp:715-726 [Conf]
  41. Bernd Becker, Rolf Drechsler
    Testability of Circuits Derived from Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:667- [Conf]
  42. Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler
    Heuristic Learning Based on Genetic Programming. [Citation Graph (0, 0)][DBLP]
    EuroGP, 2001, pp:1-10 [Conf]
  43. Rolf Drechsler
    Checking Integrity During Dynamic Reordering in Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1360-1367 [Conf]
  44. Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker
    Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1425-0 [Conf]
  45. Rolf Drechsler, Wolfgang Günther
    Generation of Optimal Universal Logic Modules. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1080-1085 [Conf]
  46. Rolf Drechsler, Wolfgang Günther, Bernd Becker
    Testability of Circuits Derived from Lattice Diagrams. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1188-1192 [Conf]
  47. Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic
    Generic Implementation of DD Packages in MVL. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1352-1359 [Conf]
  48. Wolfgang Günther, Rolf Drechsler
    ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1130-1137 [Conf]
  49. Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Verification of Designs Containing Black Boxes. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1100-1105 [Conf]
  50. Rolf Drechsler, Nicole Drechsler
    GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2003, pp:378-387 [Conf]
  51. Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
    Disjoint Sum of Product Minimization by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2004, pp:198-207 [Conf]
  52. Doina Logofatu, Rolf Drechsler
    Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2006, pp:320-331 [Conf]
  53. Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 1999, pp:108-117 [Conf]
  54. Nicole Drechsler, Wolfgang Günther, Rolf Drechsler
    Efficient Graph Coloring by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 1999, pp:30-39 [Conf]
  55. Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker
    Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 2001, pp:479-491 [Conf]
  56. Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
    Crossing Reduction by Windows Optimization. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 2002, pp:285-294 [Conf]
  57. Rolf Drechsler, Wolfgang Günther
    Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:513-518 [Conf]
  58. Wolfgang Günther, Rolf Drechsler
    Improving EAs for Sequencing Problems. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:175-180 [Conf]
  59. Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Specialized Hardware for Implementation of Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:369- [Conf]
  60. Daniel Große, Ulrich Kühne, Rolf Drechsler
    Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:308-312 [Conf]
  61. Rolf Drechsler, Junhao Shi, Görschwin Fey
    MuTaTe: an efficient design for testability technique for multiplexor based circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:80-83 [Conf]
  62. Daniel Große, Ulrich Kühne, Rolf Drechsler
    HW/SW co-verification of embedded systems using bounded model checking. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:43-48 [Conf]
  63. Wolfgang Günther, Rolf Drechsler
    Linear Transformations and Exact Minimization of BDDs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:325-330 [Conf]
  64. Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
    Utilizing don't care states in SAT-based bounded sequential problems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:264-269 [Conf]
  65. Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
    Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:178-183 [Conf]
  66. Daniel Große, Rüdiger Ebendt, Rolf Drechsler
    Improvements for constraint solving in the systemc verification library. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:493-496 [Conf]
  67. Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
    Exact sat-based toffoli network synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:96-101 [Conf]
  68. Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
    Automatic Fault Localization for Property Checking. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2006, pp:50-64 [Conf]
  69. Bernd Becker, Rolf Drechsler, Michael Theobald
    OKFDDs versus OBDDs and OFDDs. [Citation Graph (0, 0)][DBLP]
    ICALP, 1995, pp:475-486 [Conf]
  70. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-verification debugging of hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:871-876 [Conf]
  71. Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
    Debugging sequential circuits using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:204-209 [Conf]
  72. Wolfgang Günther, Rolf Drechsler
    Efficient manipulation algorithms for linearly transformed BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:50-54 [Conf]
  73. Christoph Scholl, Rolf Drechsler, Bernd Becker
    Functional simulation using binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:8-12 [Conf]
  74. Bernd Becker, Rolf Drechsler
    OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:106-110 [Conf]
  75. Rolf Drechsler, Bernd Becker
    Dynamic minimization of OKFDDs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:602-0 [Conf]
  76. Wolfgang Günther, Rolf Drechsler, Stefan Höreth
    Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:383-388 [Conf]
  77. Per Lindgren, Rolf Drechsler, Bernd Becker
    Minimization of Ordered Pseudo Kronecker Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:504-0 [Conf]
  78. Per Lindgren, Rolf Drechsler, Bernd Becker
    Synthesis of Pseudo Kronecker Lattice Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:307-310 [Conf]
  79. Rolf Drechsler, Wolfgang Günther
    History-Based Dynamic Minimization During BDD Construction. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:334-345 [Conf]
  80. Peer Johannsen, Rolf Drechsler
    Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:361-374 [Conf]
  81. Rolf Drechsler
    Synthesizing checkers for on-line verification of System-on-Chip designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:748-751 [Conf]
  82. Daniel Große, Rolf Drechsler
    Formal verification of LTL formulas for SystemC designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:245-248 [Conf]
  83. Rolf Drechsler, Marc Herbstritt, Bernd Becker
    Grouping heuristics for word-level decision diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:411-414 [Conf]
  84. Wolfgang Günther, Rolf Drechsler
    Minimization of BDDs using linear transformations based on evolutionary techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:387-390 [Conf]
  85. Frank Schmiedle, Rolf Drechsler, Bernd Becker
    Exact channel routing using symbolic representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:394-397 [Conf]
  86. Wolfgang Günther, Rolf Drechsler
    Creating hard problem instances in logic synthesis using exact minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:436-439 [Conf]
  87. Franc Brglez, Rolf Drechsler
    Design of experiments in CAD: context and new data sets for ISCAS'99. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:424-427 [Conf]
  88. Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler
    Switching activity estimation of finite state machines for low power synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:65-68 [Conf]
  89. Bernd Becker, Rolf Drechsler
    Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:65-72 [Conf]
  90. Rolf Drechsler
    Evaluation of Static Variable Ordering Heuristics for MDD Construction. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:254-260 [Conf]
  91. Rolf Drechsler
    Verification of Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:10-15 [Conf]
  92. Rolf Drechsler, Rolf Krieger, Bernd Becker
    Random Pattern Fault Simulation in Multi-Valued Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:98-103 [Conf]
  93. Rolf Drechsler, Martin Keim, Bernd Becker
    Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:66-0 [Conf]
  94. Rolf Drechsler, Martin Keim, Bernd Becker
    Fault Simulation in Sequential Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:145-0 [Conf]
  95. Rolf Drechsler, Mitchell A. Thornton
    Computation of Spectral Information from Logic Netlists. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:53-58 [Conf]
  96. Rolf Drechsler, Mitchell A. Thornton, David Wessels
    MDD-Based Synthesis of Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:41-46 [Conf]
  97. Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
    Algorithms for Taylor Expansion Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:235-240 [Conf]
  98. Görschwin Fey, Sebastian Kinder, Rolf Drechsler
    Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:361-366 [Conf]
  99. Görschwin Fey, Junhao Shi, Rolf Drechsler
    Efficiency of Multi-Valued Encoding in SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:25- [Conf]
  100. Craig M. Files, Rolf Drechsler, Marek A. Perkowski
    Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:27-0 [Conf]
  101. Daniel Große, Görschwin Fey, Rolf Drechsler
    Modeling Multi-Valued Circuits in SystemC. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:281-286 [Conf]
  102. Dragan Jankovic, Wolfgang Günther, Rolf Drechsler
    Lower Bound Sifting for MDDs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:193-198 [Conf]
  103. Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
    Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:223-228 [Conf]
  104. Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:215-0 [Conf]
  105. Sebastian Kinder, Görschwin Fey, Rolf Drechsler
    Controlling the Memory During Manipulation of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:250-255 [Conf]
  106. Per Lindgren, Rolf Drechsler, Bernd Becker
    Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:95-0 [Conf]
  107. D. Michael Miller, Rolf Drechsler
    On the Construction of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:245-253 [Conf]
  108. D. Michael Miller, Rolf Drechsler
    Augmented Sifting of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:375-382 [Conf]
  109. D. Miller, Rolf Drechsler
    Implementing a Multiple-Valued Decision Diagram Package. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:52-57 [Conf]
  110. Denis V. Popel, Rolf Drechsler
    Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:241-246 [Conf]
  111. Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
    Dynamic Re-Encoding During MDD Minimization. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:239-244 [Conf]
  112. Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
    Selection of Efficient Re-Ordering Heuristics for MDD Construction. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:299-304 [Conf]
  113. Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
    A Method for Approximate Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:447-452 [Conf]
  114. Radomir S. Stankovic, Rolf Drechsler
    Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:275-280 [Conf]
  115. Sherief Reda, Rolf Drechsler, Alex Orailoglu
    On the Relation between SAT and BDDs for Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:394-399 [Conf]
  116. Rüdiger Ebendt, Rolf Drechsler
    Quasi-Exact BDD Minimization Using Relaxed Best-First Search. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:59-64 [Conf]
  117. Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:212-217 [Conf]
  118. Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
    Multi-Output Timed Shannon Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:47-52 [Conf]
  119. Christian Genz, Rolf Drechsler
    System Exploration of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:335-342 [Conf]
  120. Ulrich Kühne, Daniel Große, Rolf Drechsler
    Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:165-170 [Conf]
  121. Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton
    Low Power Optimization Techniques for BDD Mapped Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:143-148 [Conf]
  122. Bernd Becker, Rolf Drechsler, Ralph Werchner
    On the Relation Betwen BDDs and FDDs. [Citation Graph (0, 0)][DBLP]
    LATIN, 1995, pp:72-83 [Conf]
  123. Görschwin Fey, Rolf Drechsler
    Finding Good Counter-Examples to Aid Design Verification. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:51-0 [Conf]
  124. Daniel Große, Rolf Drechsler
    Checkers for SystemC designs. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:171-178 [Conf]
  125. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-Verification Debugging of Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:42-47 [Conf]
  126. Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith
    Debugging Sequential Circuits Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:44-49 [Conf]
  127. Daniel Große, Ulrich Kühne, Rolf Drechsler
    HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:133-137 [Conf]
  128. Rolf Drechsler, Nicole Göckel, Bernd Becker
    Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:730-739 [Conf]
  129. Rolf Drechsler
    Towards Formal Verification on the System Level. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:2-5 [Conf]
  130. Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
    SyCE: An Integrated Environment for System Design in SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:258-260 [Conf]
  131. Rolf Drechsler
    Verifying Integrity of Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 1998, pp:380-389 [Conf]
  132. Rolf Drechsler, Bernd Becker, Stefan Ruppertz
    Manipulation Algorithms for K*BMDs. [Citation Graph (0, 0)][DBLP]
    TACAS, 1997, pp:4-18 [Conf]
  133. Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
    Testability of SPP Three-Level Logic Networks. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:331-336 [Conf]
  134. Nicole Drechsler, Rolf Drechsler
    Exploration of Sequential Depth by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:81-85 [Conf]
  135. Bernd Becker, Rolf Drechsler
    Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:46-50 [Conf]
  136. Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy
    (Quasi-) Linear Path Delay Fault Tests for Adders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:101-105 [Conf]
  137. Raik Brinkmann, Rolf Drechsler
    RTL-Datapath Verification using Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:741-746 [Conf]
  138. Rolf Drechsler
    Pseudo Kronecker Expressions for Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:511-513 [Conf]
  139. Rolf Drechsler, Görschwin Fey, Sebastian Kinder
    An Integrated Approach for Combining BDD and SAT Provers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:237-242 [Conf]
  140. Harry Hengster, Rolf Drechsler, Bernd Becker
    Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:123-126 [Conf]
  141. Wolfgang Günther, Rolf Drechsler
    Implementation of Read- k-times BDDs on Top of Standard BDD Packages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:173-178 [Conf]
  142. Wolfgang Günther, Rolf Drechsler
    Performance Driven Optimization for MUX based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:311-316 [Conf]
  143. Görschwin Fey, Tim Warode, Rolf Drechsler
    Reusing Learned Information in SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:69-76 [Conf]
  144. Harry Hengster, Rolf Drechsler, Bernd Becker
    On the application of local circuit transformations with special emphasis on path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:387-392 [Conf]
  145. Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
    Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:150-157 [Conf]
  146. Rolf Drechsler, Bernd Becker, Stefan Ruppertz
    The K*BMD: A Verification Data Structure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:51-59 [Journal]
  147. Bernd Becker, Rolf Drechsler, Michael Theobald
    On the Expressive Power of OKFDDs. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:11, n:1, pp:5-21 [Journal]
  148. Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
    Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:1, pp:39-58 [Journal]
  149. Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler
    Heuristic Learning Based on Genetic Programming. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2002, v:3, n:4, pp:363-388 [Journal]
  150. Bernd Becker, Rolf Drechsler, Ralph Werchner
    On the Relation between BDDs and FDDs. [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1995, v:123, n:2, pp:185-197 [Journal]
  151. Wolfgang Günther, Rolf Drechsler
    Minimization of free BDDs. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:32, n:1-2, pp:41-59 [Journal]
  152. Rolf Drechsler
    Verifying integrity of decision diagrams. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:32, n:1-2, pp:61-75 [Journal]
  153. Rolf Drechsler, Bernd Becker, Nicole Drechsler
    OKFDD minimization by genetic algorithms with application to circuit design. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:28, n:2, pp:121-139 [Journal]
  154. Rolf Drechsler, Wolfgang Günther
    History-based dynamic BDD minimization. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:51-63 [Journal]
  155. Rolf Drechsler, Wolfgang Günther, Stefan Höreth
    Minimization of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:33, n:1-2, pp:39-70 [Journal]
  156. A. Zuzek, Rolf Drechsler, Mitchell A. Thornton
    Boolean function representation and spectral characterization using AND/OR graphs. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:2, pp:101-116 [Journal]
  157. Wolfgang Günther, Rolf Drechsler
    On the computational power of linearly transformed BDDs. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2000, v:75, n:3, pp:119-125 [Journal]
  158. Daniel Große, Rolf Drechsler
    Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2003, v:45, n:4, pp:219-226 [Journal]
  159. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
    Recursive bi-partitioning of netlists for large number of partitions. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:521-528 [Journal]
  160. Rolf Drechsler, Detlef Sieling
    Binary decision diagrams in theory and practice. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:2, pp:112-136 [Journal]
  161. Rolf Drechsler
    Preudo-Kronecker Expressions for Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:987-990 [Journal]
  162. Rolf Drechsler, Bernd Becker, Andrea Jahnke
    On Variable Ordering and Decomposition Type Choice in OKFDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1398-1403 [Journal]
  163. Rolf Drechsler, Michael Theobald, Bernd Becker
    Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1294-1299 [Journal]
  164. Wolfgang Günther, Rolf Drechsler
    Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:9, pp:1196-1209 [Journal]
  165. Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
    Decision Diagram Method for Calculation of Pruned Walsh Transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:2, pp:147-157 [Journal]
  166. Frank Schmiedle, Rolf Drechsler, Bernd Becker
    Exact Routing with Search Space Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:6, pp:815-825 [Journal]
  167. Bernd Becker, Rolf Drechsler, Paul Molitor
    On the generation of area-time optimal testable adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1049-1066 [Journal]
  168. Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
    Testability of SPP Three-Level Logic Networks in Static Fault Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2241-2248 [Journal]
  169. Rolf Drechsler, Bernd Becker
    Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:1-5 [Journal]
  170. Rolf Drechsler, Bernd Becker
    Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:965-973 [Journal]
  171. Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
    Fast exact minimization of BDD's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:384-389 [Journal]
  172. Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
    Using lower bounds during dynamic BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:51-57 [Journal]
  173. Rolf Drechsler, Junhao Shi, Görschwin Fey
    Synthesis of fully testable circuits from BDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:440-443 [Journal]
  174. Rolf Drechsler, Martin Sauerhoff, Detlef Sieling
    The complexity of the inclusion operation on OFDD's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:457-459 [Journal]
  175. Rüdiger Ebendt, Rolf Drechsler
    Effect of improved lower bounds in dynamic BDD reordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:902-909 [Journal]
  176. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    An improved branch and bound algorithm for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1657-1663 [Journal]
  177. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combining ordered best-first search with branch and bound for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1515-1529 [Journal]
  178. Görschwin Fey, Rolf Drechsler
    Minimizing the number of paths in BDDs: Theory and algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:4-11 [Journal]
  179. Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
    BDD minimization using symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:81-100 [Journal]
  180. Rolf Drechsler
    Evolutionary Algorithms for VLSI CAD [book Review]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 1999, v:3, n:3, pp:251-253 [Journal]
  181. Daniel Große, Ulrich Kühne, Rolf Drechsler
    Estimating functional coverage in bounded model checking. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1176-1181 [Conf]
  182. Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
    Visualization of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:413-416 [Conf]
  183. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
    SAT-based ATPG for Path Delay Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3671-3674 [Conf]
  184. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    Integrating observability don't cares in all-solution SAT solvers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  185. Rüdiger Ebendt, Rolf Drechsler
    On the sensitivity of BDDs with respect to path-related objective functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  186. Rüdiger Ebendt, Rolf Drechsler
    A Framework for Quasi-exact Optimization Using Relaxed Best-First Search. [Citation Graph (0, 0)][DBLP]
    KI, 2006, pp:331-345 [Conf]
  187. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:181-187 [Conf]
  188. Rolf Drechsler, Görschwin Fey
    Automatic Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    SFM, 2006, pp:30-55 [Conf]
  189. Beate Muranko, Rolf Drechsler
    Technical Documentation of Software and Hardware in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:261-266 [Conf]
  190. Rüdiger Ebendt, Rolf Drechsler
    Exact BDD Minimization for Path-Related Objective Functions. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:299-315 [Conf]
  191. Beate Muranko, Rolf Drechsler
    Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:2, pp:110-0 [Journal]

  192. Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. [Citation Graph (, )][DBLP]


  193. Speeding up SAT-Based ATPG Using Dynamic Clause Activation. [Citation Graph (, )][DBLP]


  194. BDD-based synthesis of reversible logic for large functions. [Citation Graph (, )][DBLP]


  195. Computing bounds for fault tolerance using formal techniques. [Citation Graph (, )][DBLP]


  196. Reducing the number of lines in reversible circuits. [Citation Graph (, )][DBLP]


  197. Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. [Citation Graph (, )][DBLP]


  198. Automatic Generation of Complex Properties for Hardware Designs. [Citation Graph (, )][DBLP]


  199. Fast and efficient construction of BDDs by reordering based synthesis. [Citation Graph (, )][DBLP]


  200. Testability of 2-level AND/EXOR circuits. [Citation Graph (, )][DBLP]


  201. Property analysis and design understanding. [Citation Graph (, )][DBLP]


  202. Debugging of Toffoli networks. [Citation Graph (, )][DBLP]


  203. Overcoming limitations of the SystemC data introspection. [Citation Graph (, )][DBLP]


  204. Increasing the accuracy of SAT-based debugging. [Citation Graph (, )][DBLP]


  205. Verifying UML/OCL models using Boolean satisfiability. [Citation Graph (, )][DBLP]


  206. A fast untestability proof for SAT-based ATPG. [Citation Graph (, )][DBLP]


  207. Incremental SAT Instance Generation for SAT-based ATPG. [Citation Graph (, )][DBLP]


  208. On the Construction of Small Fully Testable Circuits with Low Depth. [Citation Graph (, )][DBLP]


  209. Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. [Citation Graph (, )][DBLP]


  210. Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. [Citation Graph (, )][DBLP]


  211. Robustness Check for Multiple Faults Using Formal Techniques. [Citation Graph (, )][DBLP]


  212. Fast OFDD based minimization of fixed polarity Reed-Muller expressions. [Citation Graph (, )][DBLP]


  213. BiTeS: a BDD based test pattern generator for strong robust path delay faults. [Citation Graph (, )][DBLP]


  214. Using unsatisfiable cores to debug multiple design errors. [Citation Graph (, )][DBLP]


  215. Contradictory antecedent debugging in bounded model checking. [Citation Graph (, )][DBLP]


  216. Enhancing debugging of multiple missing control errors in reversible logic. [Citation Graph (, )][DBLP]


  217. Timing Arc based logic analysis for false noise reduction. [Citation Graph (, )][DBLP]


  218. Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?. [Citation Graph (, )][DBLP]


  219. CheckSyC: an efficient property checker for RTL SystemC designs. [Citation Graph (, )][DBLP]


  220. Process variations aware robust on-chip bus architecture synthesis for MPSoCs. [Citation Graph (, )][DBLP]


  221. Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. [Citation Graph (, )][DBLP]


  222. Comparative Study by Solving the Test Compaction Problem. [Citation Graph (, )][DBLP]


  223. On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. [Citation Graph (, )][DBLP]


  224. Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. [Citation Graph (, )][DBLP]


  225. RevLib: An Online Resource for Reversible Functions and Reversible Circuits. [Citation Graph (, )][DBLP]


  226. Experimental Studies on SAT-Based ATPG for Gate Delay Faults. [Citation Graph (, )][DBLP]


  227. Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. [Citation Graph (, )][DBLP]


  228. Evaluation of Cardinality Constraints on SMT-Based Debugging. [Citation Graph (, )][DBLP]


  229. Equivalence Checking of Reversible Circuits. [Citation Graph (, )][DBLP]


  230. Reducing Reversible Circuit Cost by Adding Lines. [Citation Graph (, )][DBLP]


  231. An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions. [Citation Graph (, )][DBLP]


  232. Efficient Simulation-Based Debugging of Reversible Logic. [Citation Graph (, )][DBLP]


  233. A Basis for Formal Robustness Checking. [Citation Graph (, )][DBLP]


  234. Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. [Citation Graph (, )][DBLP]


  235. Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. [Citation Graph (, )][DBLP]


  236. WoLFram- A Word Level Framework for Formal Verification. [Citation Graph (, )][DBLP]


  237. SWORD: A SAT like prover using word level information. [Citation Graph (, )][DBLP]


  238. Co-synthesis of custom on-chip bus and memory for MPSoC architectures. [Citation Graph (, )][DBLP]


  239. Reversible Logic Synthesis with Output Permutation. [Citation Graph (, )][DBLP]


  240. Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. [Citation Graph (, )][DBLP]


  241. Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. [Citation Graph (, )][DBLP]


  242. Contradiction Analysis for Constraint-based Random Simulation. [Citation Graph (, )][DBLP]


  243. An Integrated SystemC Debugging Environment. [Citation Graph (, )][DBLP]


  244. Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. [Citation Graph (, )][DBLP]


  245. Efficient Automatic Visualization of SystemC Designs. [Citation Graph (, )][DBLP]


  246. Weighted A* search - unifying view and application. [Citation Graph (, )][DBLP]


  247. Preface. [Citation Graph (, )][DBLP]


Search in 0.012secs, Finished in 0.019secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002