The SCEAS System
Navigation Menu

Search the dblp DataBase


Bertil Svensson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Håkan Forsberg, Magnus Jonsson, Bertil Svensson
    Key Issues in Implementing an Optoelectronic Planar Free-space Architecture for Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 2003, pp:621-629 [Conf]
  2. Dennis Johnsson, Jerker Bengtsson, Bertil Svensson
    Two-level Reconfigurable Architecture for High-Performance Signal Processing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:177-183 [Conf]
  3. Zain-ul-Abdin, Bertil Svensson
    Compiling Stream-Language Applications to a Reconfigurable Array Processor. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:274-275 [Conf]
  4. Maarja Kruusmaa, Bertil Svensson
    A Low-Risk Approach to Mobile Robot Path Planning. [Citation Graph (0, 0)][DBLP]
    IEA/AIE (Vol. 2), 1998, pp:132-141 [Conf]
  5. Håkan Forsberg, Bertil Svensson, Anders Ahlander, Magnus Jonsson
    Radar Signal Processing Using Pipelines Optical Hypercube Interconnects. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:192- [Conf]
  6. Mikael Taveniku, Anders Ahlander, Magnus Jonsson, Bertil Svensson
    The VEGA Moderately Parallel MIMD, Moderately Parallel SIMD, Architectures for High Performance Array Signal Processing. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:226-232 [Conf]
  7. Magnus Jonsson, Bertil Svensson, Mikael Taveniku, Anders Ahlander
    Fiber-Ribbon Pipeline Ring Network for High-Performance Distributed Computing Systems. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1997, pp:138-143 [Conf]
  8. Anders Ahlander, Anders Åström, Bertil Svensson, Mikael Taveniku
    Meeting Engineer Efficiency Requirements in Highly Parallel Signal Processing by using Platforms. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:693-700 [Conf]
  9. Dennis Johnsson, Anders Ahlander, Bertil Svensson
    Analyzing the Advantages of Run-Time Reconfiguration in Radar Signal Processing. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:701-706 [Conf]
  10. Tomas Nordström, Bertil Svensson
    Using and Designing Massively Parallel Computers for Artificial Neural Neural Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:14, n:3, pp:260-285 [Journal]
  11. Jan Wikander, Bertil Svensson
    Editorial. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1998, v:14, n:3, pp:217-218 [Journal]
  12. Anders Ahlander, H. Hellsten, K. Lind, J. Lindgren, Bertil Svensson
    Architectural Challenges in Memory-Intensive, Real-Time Image Forming. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:35- [Conf]
  13. Zain-ul-Abdin, Bertil Svensson
    A Study of Design Efficiency with a High-Level Language for FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  14. Urban Bilstrup, Katrin Bilstrup, Bertil Svensson, Per-Arne Wiberg
    Using Dual-Radio Nodes to Enable Quality of Service in a Clustered Wireless Mesh Network. [Citation Graph (0, 0)][DBLP]
    ETFA, 2006, pp:54-61 [Conf]

  15. Manycore performance analysis using timed configuration graphs. [Citation Graph (, )][DBLP]

  16. Selecting back off algorithm in active RFID CSMA/CA based medium-access protocols. [Citation Graph (, )][DBLP]

  17. Protocols for Active RFID - The Energy Consumption Aspect. [Citation Graph (, )][DBLP]

  18. Using a CSP Based Programming Model for Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]

Search in 0.046secs, Finished in 0.046secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002