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Leonel Sousa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jorge Isidro, Luís Coelho, Kevin Ferreira, Leonel Sousa
    On the Development of a Video CODEC for Low Bitrate Communication in General Purpose Computers. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:285-288 [Conf]
  2. Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev
    The Midlifekicker Microarchitecture Evaluation Metric. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:92-100 [Conf]
  3. Nuno Roma, Leonel Sousa
    In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:170- [Conf]
  4. Shinichi Yamagiwa, Leonel Sousa, Diogo Antão
    Data buffering optimization methods toward a uniform programming interface for gpu-based applications. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:205-212 [Conf]
  5. Shinichi Yamagiwa, Leonel Sousa
    Design and implementation of a stream-based distributedcomputing platform using graphics processing units. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:197-204 [Conf]
  6. Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
    Improving SHA-2 Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:298-310 [Conf]
  7. Ricardo Chaves, Leonel Sousa
    RDSP: A RISC DSP based on Residue Number System. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:128-137 [Conf]
  8. Ricardo Chaves, Leonel Sousa
    {2n+1, sn+k, sn-1}: A New RNS Moduli Set Extension. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:210-217 [Conf]
  9. S. Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa
    Application Specific Instruction Set Processor for Adaptive Video Motion Estimation. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:160-167 [Conf]
  10. Oliver Sinnen, Leonel Sousa
    Exploiting Unused Time Slots in List Scheduling Considering Communication Contention. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:166-170 [Conf]
  11. Nuno Roma, Tiago Dias, Leonel Sousa
    Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:745-754 [Conf]
  12. Leonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez, Christian A. Morillas, Samuel F. Romero
    An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:691-700 [Conf]
  13. Oliver Sinnen, Leonel Sousa
    Scheduling Task Graphs on Arbitrary Processor Architectures Considering Contention. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 2001, pp:373-382 [Conf]
  14. Oliver Sinnen, Leonel Sousa
    Comparison of Contention Aware List Scheduling Heuristics for Cluster Computing. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2001, pp:382-390 [Conf]
  15. Nuno Roma, Leonel Sousa
    A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:253-264 [Conf]
  16. Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa
    Reconfigurable memory based AES co-processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  17. Kevin Ferreira, Shinichi Yamagiwa, Leonel Sousa, Keiichi Aoki, Koichi Wada, Luis Miguel Campos
    Distributed Shared Memory System Based on the Maestro2 High Performance Cluster Network. [Citation Graph (0, 0)][DBLP]
    ISPDC/HeteroPar, 2004, pp:91-96 [Conf]
  18. Oliver Sinnen, Leonel Sousa
    Task Scheduling: Considering the Processor Involvement in Communication. [Citation Graph (0, 0)][DBLP]
    ISPDC/HeteroPar, 2004, pp:328-335 [Conf]
  19. Ricardo Guapo, Leonel Sousa, Shinichi Yamagiwa
    On the Implementation and Evaluation of Berkeley Sockets on Maestro2 cluster computing environment. [Citation Graph (0, 0)][DBLP]
    ISPDC, 2005, pp:317-324 [Conf]
  20. Tiago Dias, Nuno Roma, Leonel Sousa
    Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:247-255 [Conf]
  21. Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
    Rescheduling for Optimized SHA-1 Calculation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:425-434 [Conf]
  22. Michel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa
    A programmable cellular neural network circuit. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:186-191 [Conf]
  23. Oliver Sinnen, Leonel Sousa
    A Platform Independent Parallelising Tool Based on Graph Theoretic Models. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2000, pp:154-167 [Conf]
  24. Leonel Sousa, Oliver Sinnen
    Synchronous Non-local Image Processing on Orthogonal Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2000, pp:453-466 [Conf]
  25. Shinichi Yamagiwa, Leonel Sousa, Kevin Ferreira, Keiichi Aoki, Masaaki Ono, Koichi Wada
    Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer. [Citation Graph (0, 0)][DBLP]
    Journal of Interconnection Networks, 2006, v:7, n:2, pp:295-318 [Journal]
  26. Oliver Sinnen, Leonel Sousa
    List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2004, v:30, n:1, pp:81-101 [Journal]
  27. Nuno Roma, Leonel Sousa
    Efficient and configurable full-search block-matching processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:12, pp:1160-0 [Journal]
  28. Oliver Sinnen, Leonel Sousa
    On Task Scheduling Accuracy: Evaluation Methodology and Results. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2004, v:27, n:2, pp:177-194 [Journal]
  29. Oliver Sinnen, Leonel Sousa
    Communication Contention in Task Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:6, pp:503-515 [Journal]
  30. Leonel Sousa
    Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:240-250 [Conf]
  31. Paulo Alexandre Crisóstomo Lopes, J. Germano, T. M. Almeida, Leonel Sousa, Moisés Simões Piedade, Filipe Cardoso, H. A. Ferreira, P. P. Freitas
    A New Handheld Biochip-based Microsystem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2379-2382 [Conf]
  32. Rodrigo Piedade, Leonel Sousa
    Configurable Embedded Core for Controlling Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:18-23 [Conf]
  33. Leonel Sousa, Moisés Simões Piedade, J. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas
    Generic Architecture Designed for Biomedical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:353-362 [Conf]

  34. Efficient Independent Component Analysis on a GPU. [Citation Graph (, )][DBLP]


  35. Iterative induced dipoles computation for molecular mechanics on GPUs. [Citation Graph (, )][DBLP]


  36. Least squares motion estimation algorithm in the compressed DCT domain for H.26x/MPEG-x video sequences. [Citation Graph (, )][DBLP]


  37. Low power microarchitecture with instruction reuse. [Citation Graph (, )][DBLP]


  38. Merged Computation for Whirlpool Hashing. [Citation Graph (, )][DBLP]


  39. Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. [Citation Graph (, )][DBLP]


  40. An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences. [Citation Graph (, )][DBLP]


  41. Preface. [Citation Graph (, )][DBLP]


  42. Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices. [Citation Graph (, )][DBLP]


  43. A Run-time Reconfigurable Processor for Video Motion Estimation. [Citation Graph (, )][DBLP]


  44. On-the-fly attestation of reconfigurable hardware. [Citation Graph (, )][DBLP]


  45. BRAM-LUT Tradeoff on a Polymorphic DES Design. [Citation Graph (, )][DBLP]


  46. Parallel LDPC Decoding on the Cell/B.E. Processor. [Citation Graph (, )][DBLP]


  47. Additive Logistic Regression Applied to Retina Modelling. [Citation Graph (, )][DBLP]


  48. Multi-core platforms for signal processing: source and channel coding. [Citation Graph (, )][DBLP]


  49. Fine-grain Parallelism Using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function. [Citation Graph (, )][DBLP]


  50. How GPUs can outperform ASICs for fast LDPC decoding. [Citation Graph (, )][DBLP]


  51. Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications. [Citation Graph (, )][DBLP]


  52. Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing. [Citation Graph (, )][DBLP]


  53. Distributed Web-based Platform for Computer Architecture Simulation. [Citation Graph (, )][DBLP]


  54. Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs. [Citation Graph (, )][DBLP]


  55. Distributed Software Platform for Automation and Control of General Anaesthesia. [Citation Graph (, )][DBLP]


  56. CaravelaMPI: Message Passing Interface for Parallel GPU-Based Applications. [Citation Graph (, )][DBLP]


  57. p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems. [Citation Graph (, )][DBLP]


  58. Massive parallel LDPC decoding on GPU. [Citation Graph (, )][DBLP]


  59. Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study. [Citation Graph (, )][DBLP]


  60. Towards a Unified Model for the Retina - Static vs Dynamic Integrate and Fire Models. [Citation Graph (, )][DBLP]


  61. A Parallel Algorithm for Advanced Video Motion Estimation on Multicore Architectures. [Citation Graph (, )][DBLP]


  62. Development and evaluation of scalable video motion estimators on GPU. [Citation Graph (, )][DBLP]


  63. Caravela: A Novel Stream-Based Distributed Computing Environment. [Citation Graph (, )][DBLP]


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