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Guido Masera: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni
    A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:51-54 [Conf]
  2. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  3. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  4. Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
    A new approach to compress the configuration information of programmable devices. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:48-51 [Conf]
  5. Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera
    Interconnection framework for high-throughput, flexible LDPC decoders. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:124-129 [Conf]
  6. F. Viglione, Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni
    A 50 Mbit/s Iterative Turbo-Decoder. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:176-180 [Conf]
  7. Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
    Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:246- [Conf]
  8. Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
    Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:332-339 [Conf]
  9. Alberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni
    High Performance Channel Model Hardware Emulator for 802.11n. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:303-304 [Conf]
  10. Guido Masera, Gianluca Piccinini, Massimo Ruo Roth, Maurizio Zamboni
    New 2 Gbit/s CMOS I/O pads. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:82-85 [Conf]
  11. Mariana-Eugenia Petre, Guido Masera
    A Parametrical Architecture for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:81-0 [Conf]
  12. Maurizio Martina, Guido Masera
    Flexible blocks for high throughput serially concatenated convolutional codes. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:184-187 [Conf]
  13. Maurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera, Giuseppe D'Angelo, Giorgio Pasquettaz
    Real-time implementation of a time-frequency analysis scheme. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:180-183 [Conf]
  14. Barbara Cerato, Guido Masera, Peter Nilsson
    Hardware architecture for matrix factorization in mimo receivers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:196-199 [Conf]
  15. Alberto Dassatti, Simone Zezza, Mario Nicola, Guido Masera
    Beyond 3G wireless communication system prototype. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:335-340 [Conf]
  16. Maurizio Martina, Guido Masera
    Low-complexity, efficient 9/7 wavelet filters implementation. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:1000-1003 [Conf]
  17. Andrea Molino, Fabrizio Vacca, Guido Masera
    Optimized CORDIC core for frequency-domain motion estimation. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:1072-1075 [Conf]
  18. Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
    Synthesis of low-leakage PD-SOI circuits with body-biasing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:287-290 [Conf]
  19. Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Noise Safety Design Methodologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:157-0 [Conf]
  20. Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
    Effects of Temperature in Deep-Submicron Global Interconnect Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:90-100 [Conf]
  21. M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:121-130 [Conf]
  22. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
    Clock Distribution Network Optimization under Self-Heating and Timing Constraints. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:198-208 [Conf]
  23. Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Hierarchical power supply noise evaluation for early power grid design prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:183-188 [Conf]
  24. Maurizio Martina, Guido Masera
    A statistical model for estimating the effect of process variations on crosstalk noise. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:115-120 [Conf]
  25. Mario Nicola, Alberto Dassatti, Guido Masera, Andrea Concil, Angelo Poloni
    Mixed hardware-software testbed for IEEE-802.11n. [Citation Graph (0, 0)][DBLP]
    TRIDENTCOM, 2006, pp:- [Conf]
  26. Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Switching Noise Analysis Framework For High Speed Logic Families. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:524-530 [Conf]
  27. Maurizio Martina, Guido Masera
    Mumford and Shah Functional: VLSI Analysis and Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 2006, v:28, n:3, pp:487-494 [Journal]
  28. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    An electromigration and thermal model of power wires for a priori high-level reliability prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:349-358 [Journal]
  29. Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:10, pp:849-857 [Journal]
  30. Giorgio Pioppo, Rashid Ansari, Ashfaq A. Khokhar, Guido Masera
    Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:3153-3156 [Conf]
  31. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  32. Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni
    VLSI architectures for turbo codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:369-379 [Journal]
  33. Guido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni
    Architectural strategies for low-power VLSI turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:279-285 [Journal]
  34. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Coupled electro-thermal modeling and optimization of clock networks. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:12, pp:1175-1185 [Journal]

  35. VLSI implementation of SISO arithmetic decoders for joint source channel coding. [Citation Graph (, )][DBLP]


  36. Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. [Citation Graph (, )][DBLP]


  37. Error resilient JPEG2000 decoding for wireless applications. [Citation Graph (, )][DBLP]


  38. A feasible VLSI engine for soft-input-soft-output for joint source channel codes. [Citation Graph (, )][DBLP]


  39. Error correcting arithmetic coding for JPEG 2000: memory and performance analysis. [Citation Graph (, )][DBLP]


  40. Decoding the Golden Code: a VLSI design [Citation Graph (, )][DBLP]


  41. Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures [Citation Graph (, )][DBLP]


  42. VLSI Architectures for WIMAX Channel Decoders [Citation Graph (, )][DBLP]


  43. A Novel VLSI Architecture of Fixed-complexity Sphere Decoder [Citation Graph (, )][DBLP]


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