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Per Larsson-Edefors: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Do Quang Minh, Lars Bengtsson, Per Larsson-Edefors
    DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 2003, pp:767-772 [Conf]
  2. Daniel Eckerbert, Per Larsson-Edefors
    Interconnect-Driven Short-Circuit Power Modeling. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:414-421 [Conf]
  3. Per Larsson-Edefors
    A Miniature Serial-Data SIMD Architecture. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10341-10344 [Conf]
  4. Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
    Accounting for the skin effect during repeater insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:32-37 [Conf]
  5. Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
    A Mixed-Mode Delay-Locked-Loop Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:261-263 [Conf]
  6. Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
    An Efficient Twin-Precision Multiplier. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:30-33 [Conf]
  7. Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson
    A low-leakage twin-precision multiplier using reconfigurable power gating. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1654-1657 [Conf]
  8. Daniel Eckerbert, Per Larsson-Edefors
    Cycle-true leakage current modeling for CMOS gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:507-510 [Conf]
  9. Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour
    A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:84-87 [Conf]
  10. Henrik Eriksson, Per Larsson-Edefors, William P. Marnane
    A regular parallel multiplier which utilizes multiple carry-propagate adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:166-169 [Conf]
  11. Henrik Eriksson, Per Larsson-Edefors
    Glitch-conscious low-power design of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:281-284 [Conf]
  12. Mindaugas Drazdziulis, Per Larsson-Edefors
    Evaluation of power cut-off techniques in the presence of gate leakage. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:745-748 [Conf]
  13. Henrik Eriksson, Per Larsson-Edefors
    Dynamic pass-transistor dot operators for efficient parallel-prefix adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:461-464 [Conf]
  14. Atila Alvandpour, Per Larsson-Edefors, Christer Svensson
    Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:245-249 [Conf]
  15. Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
    Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:557-563 [Conf]
  16. Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
    Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:185-191 [Conf]
  17. Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson
    Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:225-230 [Conf]
  18. Magnus Själander, Per Larsson-Edefors, Magnus Bjork
    A Flexible Datapath Interconnect for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:15-20 [Conf]
  19. Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson
    Overdrive Power-Gating Techniques for Total Power Minimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:125-132 [Conf]
  20. Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson
    Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:869-878 [Conf]
  21. Henrik Eriksson, Per Larsson-Edefors
    Impact of Voltage Scaling on Glitch Power Consumption. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:139-148 [Conf]
  22. Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
    On Skin Effect in On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:463-470 [Conf]
  23. Dainius Ciuplys, Per Larsson-Edefors
    On Maximum Current Estimation in CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:658-661 [Conf]
  24. Per Larsson-Edefors
    Technology mapping onto very-high-speed standard CMOS hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1137-1144 [Journal]
  25. Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
    Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:370-379 [Journal]
  26. Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, D. Johansson, M. Scholin
    Multiplier reduction tree with logarithmic logic depth and regular connectivity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Martin Thuresson, Magnus Själander, Magnus Bjork, Lars Svensson, Per Larsson-Edefors, Per Stenström
    FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:18-25 [Conf]

  28. High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. [Citation Graph (, )][DBLP]


  29. On-chip power supply noise and its implications on timing. [Citation Graph (, )][DBLP]


  30. Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. [Citation Graph (, )][DBLP]


  31. Noise Interaction Between Power Distribution Grids and Substrate. [Citation Graph (, )][DBLP]


  32. Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. [Citation Graph (, )][DBLP]


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