The SCEAS System
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Lei He:
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## Publications of Author- Lei He, Patricia Brandt
**WEAS: a web-based educational assessment system.**[Citation Graph (0, 0)][DBLP] ACM Southeast Regional Conference, 2007, pp:126-131 [Conf] - Jun Chen, Lei He
**Modeling of coplanar waveguide for buffered clock tree.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:367-372 [Conf] - Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
**A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:115-120 [Conf] - Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy
**High-level area and power-up current estimation considering rich cell library.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:899-904 [Conf] - Fei Li, Lei He, Kewal K. Saluja
**Estimation of Maximum Power-up Current.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:51-58 [Conf] - Yan Lin, Fei Li, Lei He
**Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:645-650 [Conf] - Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He
**Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:224-229 [Conf] - Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlong Hong
**CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:630-635 [Conf] - Jinjun Xiong, Lei He
**Probabilistic congestion model considering shielding for crosstalk reduction.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:739-742 [Conf] - Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He
**Constraint driven I/O planning and placement for chip-package co-design.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:207-212 [Conf] - Liang Yin, Lei He
**An efficient analytical model of coupled on-chip RLC interconnects.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:385-390 [Conf] - Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
**A wideband hierarchical circuit reduction for massively coupled interconnects.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:111-114 [Conf] - Yingjie Tang, Lei He, Xun Wang, William G. Wee
**A Model Based Contour Searching Method.**[Citation Graph (0, 0)][DBLP] BIBE, 2000, pp:347-354 [Conf] - Xun Wang, Lei He, Chia Y. Han, William G. Wee
**Deformable contour method: a constrained optimization approach.**[Citation Graph (0, 0)][DBLP] BMVC, 2002, pp:- [Conf] - Bodo Rosenhahn, Lei He, Reinhard Klette
**Automatic Human Model Generation.**[Citation Graph (0, 0)][DBLP] CAIP, 2005, pp:41-48 [Conf] - Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
**Device and architecture co-optimization for FPGA power reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:915-920 [Conf] - Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
**Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:627-632 [Conf] - Lei He, Weiping Liao, Mircea R. Stan
**System level leakage reduction considering the interdependence of temperature and leakage.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:12-17 [Conf] - Yu Hu, Yan Lin, Lei He, Tim Tuan
**Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:478-483 [Conf] - Kevin M. Lepak, Irwan Luwandi, Lei He
**Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:199-202 [Conf] - Fei Li, Yan Lin, Lei He
**FPGA power reduction using configurable dual-Vdd.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:735-740 [Conf] - Changbo Long, Lucanus Simonson, Weiping Liao, Lei He
**Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:640-645 [Conf] - Yan Lin, Lei He
**Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:720-725 [Conf] - James D. Z. Ma, Lei He
**Towards global routing with RLC crosstalk constraints.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:669-672 [Conf] - Changbo Long, Lei He
**Distributed sleep transistor network for power reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:181-186 [Conf] - Hao Yu, Lei He
**Vector potential equivalent circuit based on PEEC inversion.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:718-723 [Conf] - Hao Yu, Yiyu Shi, Lei He
**Fast analysis of structured power grid by triangularization based structure preserving model order reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:205-210 [Conf] - Yiyu Shi, Paul Mesa, Hao Yu, Lei He
**Circuit simulation based obstacle-aware Steiner routing.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:385-388 [Conf] - King Ho Tam, Lei He
**Power optimal dual-Vdd buffered tree considering buffer stations and blockages.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:497-502 [Conf] - Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He
**Clocktree RLC Extraction with Efficient Inductance Modeling.**[Citation Graph (0, 0)][DBLP] DATE, 2000, pp:522-0 [Conf] - Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak
**Scheduling of Soft Real-Time Systems for Context-Aware Applications.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:318-323 [Conf] - Jinjun Xiong, Lei He
**Full-Chip Multilevel Routing for Power and Signal Integrity.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1116-1123 [Conf] - Jinjun Xiong, King Ho Tam, Lei He
**Buffer Insertion Considering Process Variation.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:970-975 [Conf] - Deming Chen, Jason Cong, Fei Li, Lei He
**Low-power technology mapping for FPGA architectures with dual supply voltages.**[Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:109-117 [Conf] - Fei Li, Deming Chen, Lei He, Jason Cong
**Architecture evaluation for power-efficient FPGAs.**[Citation Graph (0, 0)][DBLP] FPGA, 2003, pp:175-184 [Conf] - Fei Li, Yan Lin, Lei He, Jason Cong
**Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.**[Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:42-50 [Conf] - Yan Lin, Fei Li, Lei He
**Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.**[Citation Graph (0, 0)][DBLP] FPGA, 2005, pp:199-207 [Conf] - Yan Lin, Lei He
**Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.**[Citation Graph (0, 0)][DBLP] FPGA, 2007, pp:80-88 [Conf] - Jun Chen, Lei He
**A decoupling method for analysis of coupled RLC interconnects.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:41-46 [Conf] - Min Xu, Lei He
**An efficient model for frequency-dependent on-chip inductance.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2001, pp:115-120 [Conf] - Jason Cong, Lei He
**Optimal wiresizing for interconnects with multiple sources.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:568-574 [Conf] - Jason Cong, Lei He
**An efficient approach to simultaneous transistor and interconnect sizing.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:181-186 [Conf] - Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
**Global interconnect sizing and spacing with consideration of coupling capacitance.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:628-633 [Conf] - Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
**Interconnect design for deep submicron ICs.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:478-485 [Conf] - Lei He, Tulika Mitra, Weng-Fai Wong
**Configuration bitstream compression for dynamically reconfigurable FPGAs.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:766-773 [Conf] - James D. Z. Ma, Lei He
**Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:327-332 [Conf] - Fei Li, Yan Lin, Lei He
**Vdd programmability to reduce FPGA interconnect power.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:760-765 [Conf] - Weiping Liao, Joseph M. Basile, Lei He
**Leakage power modeling and reduction with data retention.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:714-719 [Conf] - Weiping Liao, Lei He
**Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:574-580 [Conf] - Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He
**An efficient method for terminal reduction of interconnect circuits considering delay variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:821-826 [Conf] - Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
**FPGA device and architecture evaluation considering process variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:19-24 [Conf] - Jinjun Xiong, Jun Chen, James Ma, Lei He
**Post global routing RLC crosstalk budgeting.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:504-509 [Conf] - Hao Yu, Yiyu Shi, Lei He, David Smart
**A fast block structure preserving model order reduction for inverse inductance circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:7-12 [Conf] - Hao Yu, Joanna Ho, Lei He
**Simultaneous power and thermal integrity driven via stapling in 3D ICs.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:802-808 [Conf] - James D. Z. Ma, Arvind Parihar, Lei He
**Pre-routing Estimation of Shielding for RLC Signal Integrity.**[Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:553-556 [Conf] - Bin Chen, Lei He, Ping Liu
**A Morphological Edge Detector for Gray-Level Image Thresholding.**[Citation Graph (0, 0)][DBLP] ICIAR, 2005, pp:659-666 [Conf] - Lei He, Chia Y. Han, Xun Wang, Xiaokun Li, William G. Wee
**A skeleton based shape matching and recovery approach.**[Citation Graph (0, 0)][DBLP] ICIP (3), 2002, pp:789-792 [Conf] - Xiaokun Li, Feng Gao, Bryan Everding, Lei He, William G. Wee
**Error analysis, modeling, and correction for 3-D range data.**[Citation Graph (0, 0)][DBLP] ICIP (3), 2002, pp:873-876 [Conf] - Xun Wang, Lei He, William G. Wee
**Constrained optimization: a geodesic snake approach.**[Citation Graph (0, 0)][DBLP] ICIP (2), 2002, pp:77-80 [Conf] - Hao Yu, Lei He
**A sparsified vector potential equivalent circuit model for massively coupled interconnects.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:105-108 [Conf] - Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He
**Performance and RLC crosstalk driven global routing.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:65-68 [Conf] - Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
**Shielding area optimization under the solution of interconnect crosstalk.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:297-300 [Conf] - Yu Ching Chang, King Ho Tam, Lei He
**Power-optimal repeater insertion considering Vdd and Vth as design freedoms.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:137-142 [Conf] - Lei He, Mike Hutton, Tim Tuan, Steve Wilton
**Challenges and opportunities for low power FPGAs in nanometer technologies.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:90- [Conf] - Weiping Liao, Fei Li, Lei He
**Microarchitecture level power and thermal simulation considering temperature dependent leakage model.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:211-216 [Conf] - Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik
**Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:326-329 [Conf] - Yan Lin, Yu Hu, Lei He, Vijay Raghunat
**An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:168-173 [Conf] - Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
**Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:156-161 [Conf] - Fei Li, Lei He
**Maximum current estimation considering power gating.**[Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:106-111 [Conf] - Jason Cong, Lei He
**An efficient technique for device and interconnect optimization in deep submicron designs.**[Citation Graph (0, 0)][DBLP] ISPD, 1998, pp:45-51 [Conf] - Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
**Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.**[Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:78-85 [Conf] - Lei He, Kevin M. Lepak
**Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.**[Citation Graph (0, 0)][DBLP] ISPD, 2000, pp:55-60 [Conf] - Jun Chen, Lei He
**Noise driven in-package decoupling capacitor optimization for power integrity.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:94-101 [Conf] - Changbo Long, Jinjun Xiong, Lei He
**On optimal physical synthesis of sleep transistors.**[Citation Graph (0, 0)][DBLP] ISPD, 2004, pp:156-161 [Conf] - Yiyu Shi, Hao Yu, Lei He
**SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:25-32 [Conf] - Jinjun Xiong, Lei He
**Fast buffer insertion considering process variations.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:128-135 [Conf] - Jinjun Xiong, Vladimir Zolotov, Lei He
**Robust extraction of spatial correlation.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:2-9 [Conf] - Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He
**Modeling and Design of Chip-Package Interface.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:6- [Conf] - Lucanus Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He
**Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.**[Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:69-74 [Conf] - Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, Sam Nakagawa
**Instruction Prediction for Step Power Reduction.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:211-216 [Conf] - Hao Yu, Lei He
**Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:682-687 [Conf] - Lei Zhu, Lei He, Alex Collier
**MAPIS: A Mobile Amphibian Population Information System.**[Citation Graph (0, 0)][DBLP] ITCC (2), 2005, pp:254-259 [Conf] - Weiping Liao, Lei He
**Coupled Power and Thermal Simulation with Active Cooling.**[Citation Graph (0, 0)][DBLP] PACS, 2003, pp:148-163 [Conf] - Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He
**Ramp Up/Down Functional Unit to Reduce Step Power.**[Citation Graph (0, 0)][DBLP] PACS, 2000, pp:13-24 [Conf] - Fei Li, Lei He, Joseph M. Basile, Rakesh Patel, Hema Ramamurthy
**High Level Area and Current Estimation.**[Citation Graph (0, 0)][DBLP] PATMOS, 2003, pp:259-268 [Conf] - Pei Ding, Lei He, Xiang Yan, Rui Zhao, Jie Hao
**Robust Mandarin Speech Recognition for Car Navigation Interface.**[Citation Graph (0, 0)][DBLP] PCM, 2006, pp:302-309 [Conf] - Lucanus Simonson, Lei He
**Micro-architecture Performance Estimation by Formula.**[Citation Graph (0, 0)][DBLP] SAMOS, 2005, pp:192-201 [Conf] - James D. Z. Ma, Lei He
**Simultaneous signal and power routing under K model.**[Citation Graph (0, 0)][DBLP] SLIP, 2001, pp:175-182 [Conf] - Jun Chen, Lei He
**Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:92-97 [Conf] - Fei Li, Lei He, Kewal K. Saluja
**Estimation of Maximum Power-Up Current.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:51-0 [Conf] - Xun Wang, Lei He, William G. Wee
**Deformable Contour Method: A Constrained Optimization Approach.**[Citation Graph (0, 0)][DBLP] International Journal of Computer Vision, 2004, v:59, n:1, pp:87-108 [Journal] - Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
**Performance optimization of VLSI interconnect layout.**[Citation Graph (0, 0)][DBLP] Integration, 1996, v:21, n:1-2, pp:1-94 [Journal] - Lei He, Chia Y. Han, Bryan Everding, William G. Wee
**Graph matching for object recognition and recovery.**[Citation Graph (0, 0)][DBLP] Pattern Recognition, 2004, v:37, n:7, pp:1557-1560 [Journal] - Jun Chen, Lei He
**Piecewise linear model for transmission line with capacitive loading and ramp input.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:928-937 [Journal] - Jun Chen, Lei He
**Worst case crosstalk noise for nonswitching victims in high-speed buses.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1275-1283 [Journal] - Jun Chen, Lei He
**Modeling and synthesis of multiport transmission line for multichannel communication.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1664-1676 [Journal] - Jason Cong, Lei He
**Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:406-420 [Journal] - Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
**Interconnect sizing and spacing with consideration of couplingcapacitance.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1164-1169 [Journal] - Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
**Power modeling and characteristics of field programmable gate arrays.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1712-1724 [Journal] - Weiping Liao, Lei He, Kevin M. Lepak
**Temperature and supply Voltage aware performance and power modeling at microarchitecture level.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1042-1053 [Journal] - Yan Lin, Lei He
**Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2023-2034 [Journal] - Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He
**Wideband passive multiport model order reduction and realization of RLCM circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1496-1509 [Journal] - Hao Yu, Lei He
**A provably passive and cost-efficient model for inductive interconnects.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1283-1294 [Journal] - Jinjun Xiong, Lei He
**Full-chip routing optimization with RLC crosstalk budgeting.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:366-377 [Journal] - Jason Cong, Lei He
**Optimal wiresizing for interconnects with multiple sources.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:4, pp:478-511 [Journal] - Kevin M. Lepak, Min Xu, Jun Chen, Lei He
**Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:290-309 [Journal] - Xun Wang, Lei He, Yingjie Tang, William G. Wee
**A divide and conquer deformable contour method with a model based searching algorithm.**[Citation Graph (0, 0)][DBLP] IEEE Transactions on Systems, Man, and Cybernetics, Part B, 2003, v:33, n:5, pp:738-751 [Journal] - Weiping Liao, Joseph M. Basile, Lei He
**Microarchitecture-level leakage reduction with data retention.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1324-1328 [Journal] - Yan Lin, Fei Li, Lei He
**Circuits and architectures for field programmable gate array with configurable supply voltage.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1035-1047 [Journal] - Changbo Long, Lei He
**Distributed sleep transistor network for power reduction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:937-946 [Journal] - Jinjun Xiong, Lei He
**Extended global routing with RLC crosstalk constraints.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:319-329 [Journal] - Lerong Cheng, Jinjun Xiong, Lei He
**Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:250-255 [Conf] - Hao Yu, Chunta Chu, Lei He
**Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:618-621 [Conf] - Yan Lin, Lei He
**Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:636-641 [Conf] - Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
**FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.**[Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-6 [Conf] - Mike Hutton, Yan Lin, Lei He
**Placement and Timing for FPGAs Considering Variations.**[Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-7 [Conf] - Yiyu Shi, Lei He
**Empire: an efficient and compact multiple-parameterized model order reduction method.**[Citation Graph (0, 0)][DBLP] ISPD, 2007, pp:51-58 [Conf] - Hao Yu, Yu Hu, Chunchen Liu, Lei He
**Minimal skew clock embedding considering time variant temperature gradient.**[Citation Graph (0, 0)][DBLP] ISPD, 2007, pp:173-180 [Conf] - Lei He, Chuanjiang Luo, Yanfeng Geng, Feng Zhu, Yingming Hao
**Reliable Depth Map Regeneration Via a Novel Omnidirectional Stereo Sensor.**[Citation Graph (0, 0)][DBLP] ISVC (1), 2007, pp:278-287 [Conf] - Yu Hu, King Ho Tam, Tong Jing, Lei He
**Fast dual-vdd buffering based on interconnect prediction and sampling.**[Citation Graph (0, 0)][DBLP] SLIP, 2007, pp:95-102 [Conf] - Jinjun Xiong, Lei He
**Full-chip multilevel routing for power and signal integrity.**[Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:3, pp:226-234 [Journal] - Yiyu Shi, Paul Mesa, Hao Yu, Lei He
**Circuit-simulated obstacle-aware Steiner routing.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal] - Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He
**Microarchitecture Configurations and Floorplanning Co-Optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:830-841 [Journal] - Weiping Liao, Lei He
**Microarchitecture Level Interconnect Modeling Considering Layout Optimization.**[Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2005, v:1, n:3, pp:297-308 [Journal] **An Effective Segmentation for Noise-Based Image Verification Using Gamma Mixture Models.**[Citation Graph (, )][DBLP]**Incremental and on-demand random walk for iterative power distribution network analysis.**[Citation Graph (, )][DBLP]**Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.**[Citation Graph (, )][DBLP]**DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.**[Citation Graph (, )][DBLP]**Accounting for non-linear dependence using function driven component analysis.**[Citation Graph (, )][DBLP]**Non-Gaussian statistical timing analysis using second-order polynomial fitting.**[Citation Graph (, )][DBLP]**Intensity statistics-based HSI diffusion for color photo denoising.**[Citation Graph (, )][DBLP]**Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications.**[Citation Graph (, )][DBLP]**Topological routing to maximize routability for package substrate.**[Citation Graph (, )][DBLP]**FPGA area reduction by multi-output function based sequential resynthesis.**[Citation Graph (, )][DBLP]**PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.**[Citation Graph (, )][DBLP]**Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.**[Citation Graph (, )][DBLP]**Rewiring for robustness.**[Citation Graph (, )][DBLP]**A universal state-of-charge algorithm for batteries.**[Citation Graph (, )][DBLP]**QuickYield: an efficient global-search based parametric yield estimation with performance constraints.**[Citation Graph (, )][DBLP]**RALF: Reliability Analysis for Logic Faults - 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