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Christoph W. Kessler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mikhail Chalabine, Christoph W. Kessler
    Parallelisation of Sequential Programs by Invasive Composition and Aspect Weaving. [Citation Graph (0, 0)][DBLP]
    APPT, 2005, pp:131-140 [Conf]
  2. Andrzej Bednarski, Christoph W. Kessler
    Optimal Integrated VLIW Code Generation with Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:461-472 [Conf]
  3. Paul H. J. Kelly, Sergei Gorlatch, Christoph W. Kessler, Daniel J. Quinlan
    Topic 10: Parallel Programming: Models, Methods and Programming Languages. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:614- [Conf]
  4. Mikhail Chalabine, Christoph W. Kessler
    Crosscutting Concerns in Parallelization by Invasive Software Composition and Aspect Weaving. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]
  5. Mikhail Chalabine, Christoph W. Kessler
    A Formal Framework for Automated Round-Trip Software Engineering in Static Aspect Weaving and Transformations. [Citation Graph (0, 0)][DBLP]
    ICSE, 2007, pp:137-146 [Conf]
  6. Håkan Mattsson, Christoph W. Kessler
    Towards a Bulk-Synchronous Distributed Shared Memory Programming Environment for Grids. [Citation Graph (0, 0)][DBLP]
    PARA, 2004, pp:519-526 [Conf]
  7. Christoph W. Kessler
    Pattern-driven automatic program transformation and parallelization. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:76-83 [Conf]
  8. Christoph W. Kessler
    A practical access to the theory of parallel algorithms. [Citation Graph (0, 0)][DBLP]
    SIGCSE, 2004, pp:397-401 [Conf]
  9. Christoph Kessler, Peter Fritzson, Mattias Eriksson
    NestStepModelica - Mathematical Modeling and Bulk-Synchronous Parallel Simulation. [Citation Graph (0, 0)][DBLP]
    PARA, 2006, pp:1006-1015 [Conf]

  10. Hybrid Parallel Sort on the Cell Processor. [Citation Graph (, )][DBLP]


  11. 05101 Executive Summary - Scheduling for Parallel Architectures: Theory, Applications, Challenges. [Citation Graph (, )][DBLP]


  12. 05101 Abstracts Collection - Scheduling for Parallel Architectures: Theory, Applications, Challenges. [Citation Graph (, )][DBLP]


  13. Optimized Pipelined Parallel Merge Sort on the Cell BE. [Citation Graph (, )][DBLP]


  14. Optimized On-Chip-Pipelined Mergesort on the Cell/B.E. [Citation Graph (, )][DBLP]


  15. Integrated Modulo Scheduling for Clustered VLIW Architectures. [Citation Graph (, )][DBLP]


  16. Message from the PDSEC-09 workshop chairs. [Citation Graph (, )][DBLP]


  17. A Framework for Performance-Aware Composition of Explicitly Parallel Components. [Citation Graph (, )][DBLP]


  18. Optimal vs. heuristic integrated code generation for clustered VLIW architectures. [Citation Graph (, )][DBLP]


  19. Classification and generation of schedules for VLIW processors. [Citation Graph (, )][DBLP]


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