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Dong Xiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jingli Zhou, Dong Xiang, Shengsheng Yu, Lin Zhong, Jian Gu
    A Method of Data Assignment on Heterogeneous Disk System. [Citation Graph (0, 0)][DBLP]
    APPT, 2003, pp:162-166 [Conf]
  2. Dong Xiang, Ming-Jing Chen, Hideo Fujiwara
    Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:126-131 [Conf]
  3. Dong Xiang, Ming-Jing Chen, Kai-Wei Li, Yu-Liang Wu
    Scan-Based BIST Using an Improved Scan Forest Architecture. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:88-93 [Conf]
  4. Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
    Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:12-17 [Conf]
  5. Dong Xiang, Shan Gu, Hideo Fujiwara
    Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:86-0 [Conf]
  6. Dong Xiang, Shan Gu, Hideo Fujiwara
    Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:300-305 [Conf]
  7. Dong Xiang, Kai-Wei Li, Hideo Fujiwara
    Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:318-323 [Conf]
  8. Dong Xiang, Yi Xu
    A Multiple Phase Partial Scan Design Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:17-22 [Conf]
  9. Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu
    A cost-effective scan architecture for scan testing with non-scan test power and test application cost. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:744-747 [Conf]
  10. Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel
    Partial Scan Design Based on Circuit State Information. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:807-812 [Conf]
  11. Dong Xiang, Yi Xu
    Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:154-160 [Conf]
  12. Dong Xiang, Ai Chen, Jie Wu
    Fault-Tolerant Broadcasting in Hypercubes via Local Safety Information. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2002, pp:31-36 [Conf]
  13. Dong Xiang, Ai Chen
    Fault-Tolerant Routing in 2D Tori or Meshes Using Limited-Global-Safety Information. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:231-238 [Conf]
  14. Dong Xiang, Jia-Guang Sun, Jie Wu, Krishnaiyan Thulasiraman
    Fault-Tolerant Routing in Meshes/Tori Using Planarly Constructed Fault Blocks. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:577-584 [Conf]
  15. Dong Xiang, Ai Chen
    Partial Path Set up for Fault Tolerant Routing in Hypercubes. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:275- [Conf]
  16. Hui Wang, Dong Xiang, Guanghong Duan, Jie Song
    A Hybrid Heuristic Approach for Disassembly/Recycle Applications. [Citation Graph (0, 0)][DBLP]
    ISDA (1), 2006, pp:985-995 [Conf]
  17. Dong Xiang, Janak H. Patel
    A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:548-557 [Conf]
  18. Dong Xiang, Yi Xu, Hideo Fujiwara
    Non-scan design for testability for synchronous sequential circuits based on conflict analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:520-529 [Conf]
  19. Grace Wahba, Xiwu Lin, Fangyu Gao, Dong Xiang, Ronald Klein, Barbara Klein
    The Bias-Variance Tradeoff and the Randomized GACV. [Citation Graph (0, 0)][DBLP]
    NIPS, 1998, pp:620-626 [Conf]
  20. Wenke Lee, Dong Xiang
    Information-Theoretic Measures for Anomaly Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Security and Privacy, 2001, pp:130-143 [Conf]
  21. Dong Xiang, Dao-zheng Wei
    An Optimal Design for Parallel Test Generation Based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:297-300 [Conf]
  22. Dong Xiang, Yi Xu
    Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:82-87 [Conf]
  23. Monica Benito, Joel Parker, Quan Du, Junyuan Wu, Dong Xiang, Charles M. Perou, James Stephen Marron
    Adjustment of systematic microarray data biases. [Citation Graph (0, 0)][DBLP]
    Bioinformatics, 2004, v:20, n:1, pp:105-114 [Journal]
  24. Dong Xiang
    Fault-tolerant routing in hypercubes using partial path set-up. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2006, v:22, n:7, pp:812-819 [Journal]
  25. Dong Xiang, Ai Chen, Jie Wu
    Local-Safety-Information-Based Fault-Tolerant Broadcasting in Hypercubes. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:3, pp:467-478 [Journal]
  26. Dong Xiang, Ai Chen, Jie Wu
    Local-Safety-Information-Based Broadcasting in Hypercube Multicomputers with Node and Link Faults. [Citation Graph (0, 0)][DBLP]
    Journal of Interconnection Networks, 2001, v:2, n:3, pp:365-378 [Journal]
  27. Dong Xiang, Ai Chen, Jia-Guang Sun
    Fault-tolerant multicasting in hypercubes using local safety information. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:2, pp:248-256 [Journal]
  28. Dong Xiang, Ai Chen, Jiaguang Sun
    Fault-tolerant routing and multicasting in hypercubes using a partial path set-up. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2005, v:31, n:3-4, pp:389-411 [Journal]
  29. Dong Xiang, Janak H. Patel
    Partial Scan Design Based on Circuit State Information and Functional Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:276-287 [Journal]
  30. Dong Xiang, Yi Xu, Hideo Fujiwara
    Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:1063-1075 [Journal]
  31. Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara
    Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:4, pp:557-562 [Journal]
  32. Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
    Improving test effectiveness of scan-based BIST by scan chain partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:916-927 [Journal]
  33. Dong Xiang, Hideo Fujiwara
    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1105-1113 [Journal]
  34. Dong Xiang
    Fault-Tolerant Routing in Hypercube Multicomputers Using Local Safety Information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:9, pp:942-951 [Journal]
  35. Dong Xiang, Yueli Zhang, Yi Pan, Jie Wu
    Deadlock-Free Adaptive Routing in Meshes Based on Cost-Effective Deadlock Avoidance Schemes. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:41- [Conf]
  36. Dong Xiang, Mingjing Chen, Hideo Fujiwara
    Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:12, pp:1619-1628 [Journal]
  37. Dong Xiang, Ai Chen, Jie Wu
    Reliable broadcasting in wormhole-routed hypercube-connected networks using local safety information. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:2, pp:245-256 [Journal]

  38. Conflict driven scan chain configuration for high transition fault coverage and low test power. [Citation Graph (, )][DBLP]


  39. Compact Test Generation for Small-Delay Defects Using Testable-Path Information. [Citation Graph (, )][DBLP]


  40. A power-effective scan architecture using scan flip-flops clustering and post-generation filling. [Citation Graph (, )][DBLP]


  41. Deadlock-Free Adaptive Routing in 2D Tori with a New Turn Model. [Citation Graph (, )][DBLP]


  42. Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. [Citation Graph (, )][DBLP]


  43. Deadlock-Free Fully Adaptive Routing in 2-Dimensional Tori Based on New Virtual Network Partitioning Scheme. [Citation Graph (, )][DBLP]


  44. An online advertisement platform based on image content bidding. [Citation Graph (, )][DBLP]


  45. Visiads: A vision-based advertising platform for camera phones. [Citation Graph (, )][DBLP]


  46. Deadlock-Free Fully Adaptive Routing in Tori Based on a New Virtual Network Partitioning Scheme. [Citation Graph (, )][DBLP]


  47. New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. [Citation Graph (, )][DBLP]


  48. A Unified Solution to Scan Test Volume, Time, and Power Minimization. [Citation Graph (, )][DBLP]


  49. A Compression Framework for Personal Image Used in Mobile RFID System. [Citation Graph (, )][DBLP]


  50. A Density Adaptive Routing Protocol for Large-Scale Ad Hoc Networks. [Citation Graph (, )][DBLP]


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