The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Rahul Nagpal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rahul Nagpal, Anasua Bhowmik
    Criticality Based Speculation Control for Speculative Multithreaded Architectures. [Citation Graph (0, 0)][DBLP]
    APPT, 2005, pp:31-40 [Conf]
  2. Rahul Nagpal, Y. N. Srikant
    Integrated temporal and spatial scheduling for extended operand clustered VLIW processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:457-470 [Conf]
  3. Rahul Nagpal, Y. N. Srikant
    Compiler-assisted leakage energy optimization for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:233-241 [Conf]
  4. Rahul Nagpal, Y. N. Srikant
    Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:497-508 [Conf]
  5. Rahul Nagpal, Anasua Bhowmik
    Criticality Driven Energy Aware Speculation for Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    HiPC, 2005, pp:19-28 [Conf]
  6. Rahul Nagpal, Y. N. Srikant
    A Graph Matching Based Integrated Scheduling Framework for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2004, pp:530-537 [Conf]
  7. Rahul Nagpal, Arvind Madan, Amrutur Bhardwaj, Y. N. Srikant
    INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:238-247 [Conf]

  8. Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture. [Citation Graph (, )][DBLP]


  9. Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures. [Citation Graph (, )][DBLP]


  10. Detecting and tolerating asymmetric races. [Citation Graph (, )][DBLP]


  11. Register File Energy Optimization for Snooping Based Clustered VLIW Architectures. [Citation Graph (, )][DBLP]


Search in 0.011secs, Finished in 0.012secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002