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Trong-Yen Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pao-Ann Hsiung, Trong-Yen Lee, Feng-Shi Su
    Formal Synthesis and Code Generation of Real-Time Embedded Software using Time-Extended Quasi-Static Scheduling. [Citation Graph (0, 0)][DBLP]
    APSEC, 2002, pp:395-404 [Conf]
  2. Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen
    Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks. [Citation Graph (0, 0)][DBLP]
    APSEC, 2001, pp:71-78 [Conf]
  3. Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang
    RCGES: Retargetable Code Generation for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:415-425 [Conf]
  4. Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
    TCN: Scalable Hierarchical Hypercubes. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2002, pp:11-16 [Conf]
  5. Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen
    A new CCII-based pipelined analog to digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6170-6173 [Conf]
  6. Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang
    A new low-power turbo decoder using HDA-DHDD stopping iteration. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1040-1043 [Conf]
  7. Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen
    VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Symposium on Object-Oriented Real-Time Distributed Computing, 2002, pp:322-329 [Conf]
  8. Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
    A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:2982-2987 [Conf]
  9. Pao-Ann Hsiung, Cheng-Yi Lin, Trong-Yen Lee
    Quasi-Dynamic Scheduling for the Synthesis of Real-Time Embedded Software with Local and Global Deadlines. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2003, pp:229-243 [Conf]
  10. Trong-Yen Lee, Pao-Ann Hsiung, I-Mu Wu, Feng-Shi Su
    RESS: Real-Time Embedded Software Synthesis and Prototyping Methodology. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2003, pp:529-544 [Conf]
  11. Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
    Software Platform for Embedded Software Development. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2003, pp:545-557 [Conf]
  12. Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai
    Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    ICICIC (2), 2006, pp:515-518 [Conf]
  13. Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee
    Zero-Skew Driven for RLC Clock Tree Construction in SoC. [Citation Graph (0, 0)][DBLP]
    ICITA (1), 2005, pp:561-566 [Conf]
  14. Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
    Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    TOOLS (24), 1997, pp:284-293 [Conf]
  15. Pao-Ann Hsiung, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
    SESAG: an object-oriented application framework for real-time systems. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2005, v:35, n:10, pp:899-921 [Journal]
  16. Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen
    ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:109-135 [Journal]
  17. Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
    VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2004, v:30, n:10, pp:656-674 [Journal]
  18. Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao
    Coupling aware RLC-based clock routings for crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  19. Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao
    A single chip image sensor embedded smooth spatial filter with A/D conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  20. Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu
    Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2006, v:22, n:6, pp:1585-1599 [Journal]

  21. An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. [Citation Graph (, )][DBLP]


  22. Antenna Violation Avoidance/Fixing for X-clock routing. [Citation Graph (, )][DBLP]


  23. Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. [Citation Graph (, )][DBLP]


  24. Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. [Citation Graph (, )][DBLP]


  25. X-clock routing based on pattern matching. [Citation Graph (, )][DBLP]


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