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R. Rodríguez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. R. G. Durán, L. Hervella-Nieto, E. Liberman, R. Rodríguez, J. Solomin
    Approximation of the vibration modes of a plate by Reissner-Mindlin equations. [Citation Graph (0, 0)][DBLP]
    Math. Comput., 1999, v:68, n:228, pp:1447-1463 [Journal]
  2. R. Rodríguez, M. Porti, M. Nafría, X. Aymerich
    Influence of a low field with opposite polarity to the stress on the degradation of 4.5 nm thick SiO2 films. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:7, pp:1011-1013 [Journal]
  3. R. Rodríguez, James H. Stathis, Barry P. Linder, S. Kowalczyk, C. T. Chuang, R. V. Joshi, G. Northrop, K. Bernstein, A. J. Bhavnagarwala, Salvatore Lombardo
    Analysis of the effect of the gate oxide breakdown on SRAM stability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:9-11, pp:1445-1448 [Journal]
  4. R. Rodríguez, James H. Stathis, Barry P. Linder, R. V. Joshi, C. T. Chuang
    Influence and model of gate oxide breakdown on CMOS inverters. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1439-1444 [Journal]
  5. James H. Stathis, Barry P. Linder, R. Rodríguez, Salvatore Lombardo
    Reliability of ultra-thin oxides in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1353-1360 [Journal]
  6. James H. Stathis, R. Rodríguez, Barry P. Linder
    Circuit implications of gate oxide breakdown. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1193-1197 [Journal]
  7. R. Fernández, R. Rodríguez, M. Nafría, X. Aymerich
    Influence of oxide breakdown position and device aspect ratio on MOSFET's output characteristics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:5-6, pp:861-864 [Journal]
  8. R. Fernández, R. Rodríguez, M. Nafría, X. Aymerich, B. Kaczer, G. Groeseneken
    FinFET and MOSFET preliminary comparison of gate oxide reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1608-1611 [Journal]
  9. Eva M. Ortigosa, Antonio Cañas, R. Rodríguez, Javier Díaz, Sonia Mota
    Towards an Optimal Implementation of MLP in FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:46-51 [Conf]

  10. Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. [Citation Graph (, )][DBLP]


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