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Hritam Dutta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hritam Dutta, Frank Hannig, Jürgen Teich
    Controller Synthesis for Mapping Partitioned Programs on Array Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:176-190 [Conf]
  2. Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
    A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:331-340 [Conf]
  3. Frank Hannig, Hritam Dutta, Jürgen Teich
    Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  4. Hritam Dutta, Frank Hannig, Jürgen Teich
    Hierarchical Partitioning for Piecewise Linear Algorithms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:153-160 [Conf]
  5. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  6. Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
    Automatic FIR Filter Generation for FPGAs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:51-61 [Conf]
  7. Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
    Massively Parallel Processor Architectures: A Co-design Approach. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:61-68 [Conf]
  8. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
    Efficient control generation for mapping nested loop programs onto processor arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:300-309 [Journal]

  9. Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. [Citation Graph (, )][DBLP]

  10. Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. [Citation Graph (, )][DBLP]

  11. Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. [Citation Graph (, )][DBLP]

  12. Impact of Loop Tiling on the Controller Logic of Acceleration Engines. [Citation Graph (, )][DBLP]

  13. Model-based synthesis and optimization of static multi-rate image processing algorithms. [Citation Graph (, )][DBLP]

  14. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. [Citation Graph (, )][DBLP]

  15. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]

  16. Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. [Citation Graph (, )][DBLP]

  17. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. [Citation Graph (, )][DBLP]

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