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Frank Hannig: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hritam Dutta, Frank Hannig, Jürgen Teich
    Controller Synthesis for Mapping Partitioned Programs on Array Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:176-190 [Conf]
  2. Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
    Modeling of Interconnection Networks in Massively Parallel Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:268-282 [Conf]
  3. Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
    A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:331-340 [Conf]
  4. Frank Hannig, Jürgen Teich
    Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:17-27 [Conf]
  5. Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich
    Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:9-14 [Conf]
  6. Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
    A Generic Framework for Rapid Prototyping of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:189-195 [Conf]
  7. Frank Hannig, Jürgen Teich
    Output Serialization for FPGA-based and Coarse-grained Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:78-84 [Conf]
  8. Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
    Defragmenting the Module Layout of a Partially Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:92-104 [Conf]
  9. Frank Hannig, Hritam Dutta, Jürgen Teich
    Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  10. Frank Hannig, Jürgen Teich
    Design Space Exploration for Massively Parallel Processor Arrays. [Citation Graph (0, 0)][DBLP]
    PaCT, 2001, pp:51-65 [Conf]
  11. Frank Hannig, Jürgen Teich
    Dynamic Piecewise Linear/Regular Algorithms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:79-84 [Conf]
  12. Hritam Dutta, Frank Hannig, Jürgen Teich
    Hierarchical Partitioning for Piecewise Linear Algorithms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:153-160 [Conf]
  13. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  14. Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
    A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:31-37 [Conf]
  15. Marcus Bednara, Frank Hannig, Jürgen Teich
    Generation of Distributed Loop Control. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:154-170 [Conf]
  16. Alexey Kupriyanov, Frank Hannig, Jürgen Teich
    High-Speed Event-Driven RTL Compiled Simulation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:519-529 [Conf]
  17. Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
    Automatic FIR Filter Generation for FPGAs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:51-61 [Conf]
  18. Frank Hannig, Jürgen Teich
    Energy estimation of nested loop programs. [Citation Graph (0, 0)][DBLP]
    SPAA, 2002, pp:149-150 [Conf]
  19. Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
    Massively Parallel Processor Architectures: A Co-design Approach. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:61-68 [Conf]
  20. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
    Efficient control generation for mapping nested loop programs onto processor arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:300-309 [Journal]

  21. Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. [Citation Graph (, )][DBLP]

  22. Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. [Citation Graph (, )][DBLP]

  23. Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. [Citation Graph (, )][DBLP]

  24. Impact of Loop Tiling on the Controller Logic of Acceleration Engines. [Citation Graph (, )][DBLP]

  25. Model-based synthesis and optimization of static multi-rate image processing algorithms. [Citation Graph (, )][DBLP]

  26. Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. [Citation Graph (, )][DBLP]

  27. Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]

  28. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. [Citation Graph (, )][DBLP]

  29. Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]

  30. Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. [Citation Graph (, )][DBLP]

  31. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]

  32. System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. [Citation Graph (, )][DBLP]

  33. Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  34. Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. [Citation Graph (, )][DBLP]

  35. Efficient event-driven simulation of parallel processor architectures. [Citation Graph (, )][DBLP]

  36. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. [Citation Graph (, )][DBLP]

  37. Defragmenting the Module Layout of a Partially Reconfigurable Device [Citation Graph (, )][DBLP]

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