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Jürgen Teich: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hritam Dutta, Frank Hannig, Jürgen Teich
    Controller Synthesis for Mapping Partitioned Programs on Array Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:176-190 [Conf]
  2. Ali Ahmadinia, Christophe Bobda, Jürgen Teich
    A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS, 2004, pp:125-139 [Conf]
  3. Christophe Bobda, Ali Ahmadinia, Jürgen Teich
    Generation of Distributed Arithmetic Designs for Reconfigurable Application. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:205-214 [Conf]
  4. Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich
    An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:202-216 [Conf]
  5. Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich
    A Flexible Reconfiguration Manager for the Erlangen Slot Machine. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:183-194 [Conf]
  6. Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
    Modeling of Interconnection Networks in Massively Parallel Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:268-282 [Conf]
  7. Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka
    Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:299-308 [Conf]
  8. Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
    A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:331-340 [Conf]
  9. Frank Hannig, Jürgen Teich
    Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:17-27 [Conf]
  10. Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich
    Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:9-14 [Conf]
  11. Jürgen Teich, Lothar Thiele, Li Zhang
    Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:131-144 [Conf]
  12. Jürgen Teich, Philipp W. Kutter, Ralph Weper
    Description and Simulation of Microprocessor Instruction Sets Using ASMs. [Citation Graph (0, 0)][DBLP]
    Abstract State Machines, 2000, pp:266-286 [Conf]
  13. Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich
    A system-level approach to hardware reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:298-301 [Conf]
  14. Thilo Streichert, Christian Haubelt, Jürgen Teich
    Online hardware/software partitioning in networked embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:982-985 [Conf]
  15. Dirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper
    Efficient architecture/compiler co-exploration for ASIPs. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:27-34 [Conf]
  16. Dirk Fischer, Jürgen Teich, Ralph Weper, Uwe Kastens, Michael Thies
    Design space characterization for architecture/compiler co-exploration. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:108-115 [Conf]
  17. Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert
    A joined architecture/compiler design environment for ASIPs. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:26-33 [Conf]
  18. Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
    A Generic Framework for Rapid Prototyping of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:189-195 [Conf]
  19. Dirk Koch, Jürgen Teich
    Platform-independent methodology for partial reconfiguration. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:398-403 [Conf]
  20. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
    Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:243-248 [Conf]
  21. Michael Eisenring, Jürgen Teich
    Domain-specific interface generation from dataflow specifications. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:43-47 [Conf]
  22. Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    Scheduling hardware/software systems using symbolic techniques. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:173-177 [Conf]
  23. Jürgen Teich, Tobias Blickle, Lothar Thiele
    An evolutionary approach to system-level synthesis. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:167-172 [Conf]
  24. Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
    3D exploration of software schedules for DSP algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:168-172 [Conf]
  25. Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele
    Combining multiple models of computation for scheduling and allocation. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:9-13 [Conf]
  26. Jürgen Teich
    Are current ESL tools meeting the requirements of advanced embedded systems? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:166- [Conf]
  27. Christian Schwarz, Jürgen Teich, Alek Vainshtein, Emo Welzl, Brian L. Evans
    Minimal Enclosing Parallelogram with Application. [Citation Graph (0, 0)][DBLP]
    Symposium on Computational Geometry, 1995, pp:0-0 [Conf]
  28. Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich
    Representation of Function Variants for Embedded System Optimization and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:517-522 [Conf]
  29. Sanaz Mostaghim, Jürgen Teich
    A New Approach on Many Objective Diversity Measurement. [Citation Graph (0, 0)][DBLP]
    Practical Approaches to Multi-Objective Optimization, 2005, pp:- [Conf]
  30. Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
    Optimal FPGA module placement with temporal precedence constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:658-667 [Conf]
  31. Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich
    Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11110-11111 [Conf]
  32. Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien
    SAT-Based Techniques in System Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11168-11169 [Conf]
  33. Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
    System Design for Flexibility. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:854-861 [Conf]
  34. Thilo Streichert, Christian Haubelt, Jürgen Teich
    Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:894-895 [Conf]
  35. M. Streubühr, J. Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf
    Task-accurate performance modeling in SystemC for real-time multi-processor architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:480-481 [Conf]
  36. Jürgen Teich, Markus Köster
    (Self-)reconfigurable Finite State Machines: Theory and Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:559-567 [Conf]
  37. Christian Haubelt, Jürgen Gamenik, Jürgen Teich
    Initial Population Construction for Convergence Improvement of MOEAs. [Citation Graph (0, 0)][DBLP]
    EMO, 2005, pp:191-205 [Conf]
  38. Christian Haubelt, Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi
    Solving Hierarchical Optimization Problems Using MOEAs. [Citation Graph (0, 0)][DBLP]
    EMO, 2003, pp:162-176 [Conf]
  39. Oliver Schütze, Sanaz Mostaghim, Michael Dellnitz, Jürgen Teich
    Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. [Citation Graph (0, 0)][DBLP]
    EMO, 2003, pp:118-132 [Conf]
  40. Jürgen Teich
    Pareto-Front Exploration with Uncertain Objectives. [Citation Graph (0, 0)][DBLP]
    EMO, 2001, pp:314-328 [Conf]
  41. Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
    Symbolic Archive Representation for a Fast Nondominance Test. [Citation Graph (0, 0)][DBLP]
    EMO, 2006, pp:111-125 [Conf]
  42. Frank Hannig, Jürgen Teich
    Output Serialization for FPGA-based and Coarse-grained Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:78-84 [Conf]
  43. Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
    Defragmenting the Module Layout of a Partially Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:92-104 [Conf]
  44. Dirk Koch, Matthiaas Koerber, Jürgen Teich
    Searching RC5-Keys with Distributed Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:42-48 [Conf]
  45. Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner
    Topic 18: Embedded Parallel Systems. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:1179- [Conf]
  46. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:319-320 [Conf]
  47. Dirk Koch, Christian Haubelt, Jürgen Teich
    Efficient hardware checkpointing: concepts, overhead analysis, and implementation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:188-196 [Conf]
  48. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:847-851 [Conf]
  49. Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:153-158 [Conf]
  50. Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
    A Dynamic NoC Approach for Communication in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1032-1036 [Conf]
  51. Michael Eisenring, Jürgen Teich
    Interfacing Hardware and Software. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:520-524 [Conf]
  52. Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich
    Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:478-487 [Conf]
  53. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
    The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:37-42 [Conf]
  54. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
    Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    GECCO (2), 2004, pp:383-384 [Conf]
  55. Thomas Schlichter, Christian Haubelt, Jürgen Teich
    Improving EA-based design space exploration by utilizing symbolic feasibility tests. [Citation Graph (0, 0)][DBLP]
    GECCO, 2005, pp:1945-1952 [Conf]
  56. Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele
    SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2005, pp:693-697 [Conf]
  57. Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState - an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:558-565 [Conf]
  58. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele
    Representation of process mode correlation for scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:54-61 [Conf]
  59. F. Cieslok, H. Esau, Jürgen Teich
    EXPLORA - Generic Design Space Exploration during Embedded System Synthesis. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:215-226 [Conf]
  60. Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
    A New Approach for On-line Placement on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  61. Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
    Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  62. Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich
    Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  63. Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich
    A High Performance VLIW Processor for Finite Field Arithmetic. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:189- [Conf]
  64. Frank Hannig, Hritam Dutta, Jürgen Teich
    Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  65. Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
    Packet Routing in Dynamically Changing Networks on Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  66. Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
    FPGA designs of parallel high performance GF(2233) multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:268-271 [Conf]
  67. Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
    Tradeoff analysis of FPGA based elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:797-800 [Conf]
  68. Jürgen Teich, Lothar Thiele, Edward A. Lee
    Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:156-161 [Conf]
  69. Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich
    Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:309-316 [Conf]
  70. Frank Hannig, Jürgen Teich
    Design Space Exploration for Massively Parallel Processor Arrays. [Citation Graph (0, 0)][DBLP]
    PaCT, 2001, pp:51-65 [Conf]
  71. Frank Hannig, Jürgen Teich
    Dynamic Piecewise Linear/Regular Algorithms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:79-84 [Conf]
  72. Hritam Dutta, Frank Hannig, Jürgen Teich
    Hierarchical Partitioning for Piecewise Linear Algorithms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:153-160 [Conf]
  73. Jürgen Teich, Sándor P. Fekete, Jörg Schepers
    Compile-time Optimization of Dynamic Hardware Reconfigurations. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1097-1103 [Conf]
  74. Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
    Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. [Citation Graph (0, 0)][DBLP]
    PPSN, 1998, pp:885-896 [Conf]
  75. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  76. Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
    A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:31-37 [Conf]
  77. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:84-90 [Conf]
  78. Marcus Bednara, Frank Hannig, Jürgen Teich
    Generation of Distributed Loop Control. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:154-170 [Conf]
  79. Alexey Kupriyanov, Frank Hannig, Jürgen Teich
    High-Speed Event-Driven RTL Compiled Simulation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:519-529 [Conf]
  80. Christian Haubelt, Dirk Koch, Jürgen Teich
    Basic OS Support for Distributed Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:30-38 [Conf]
  81. Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
    Flexibility/Cost-Tradeoffs of Platform-Based Systems. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:38-56 [Conf]
  82. Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
    Automatic FIR Filter Generation for FPGAs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:51-61 [Conf]
  83. Jürgen Teich, Shuvra S. Bhattacharyya
    Analysis of Dataflow Programs with Interval-Limited Data-Rates. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:507-518 [Conf]
  84. Jürgen Teich, Lothar Thiele
    Exact Partitioning of Affine Dependence Algorithms. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:135-153 [Conf]
  85. Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
    Task scheduling for heterogeneous reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:22-27 [Conf]
  86. Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich
    Dynamic task binding for hardware/software reconfigurable networks. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:38-43 [Conf]
  87. Christian Haubelt, Dirk Koch, Jürgen Teich
    ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:343-348 [Conf]
  88. Frank Hannig, Jürgen Teich
    Energy estimation of nested loop programs. [Citation Graph (0, 0)][DBLP]
    SPAA, 2002, pp:149-150 [Conf]
  89. Ali Ahmadinia, Jürgen Teich
    Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:118-122 [Conf]
  90. Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
    Higher-Dimensional Packing with Order Constraints. [Citation Graph (0, 0)][DBLP]
    WADS, 2001, pp:300-312 [Conf]
  91. Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
    Higher-Dimensional Packing with Order Constraints [Citation Graph (0, 0)][DBLP]
    CoRR, 2003, v:0, n:, pp:- [Journal]
  92. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices [Citation Graph (0, 0)][DBLP]
    CoRR, 2004, v:0, n:, pp:- [Journal]
  93. Dirk Fischer, Jürgen Teich, Ralph Weper, Michael Thies
    BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:3, pp:353-0 [Journal]
  94. Lothar Thiele, Jürgen Teich, Karsten Strehl
    Regular state machines. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2000, v:15, n:3-4, pp:265-300 [Journal]
  95. Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin
    Performance analysis and optimization of mixed asynchronous synchronous systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:473-484 [Journal]
  96. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
    Systematic integration of parameterized local search into evolutionary algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2004, v:8, n:2, pp:137-155 [Journal]
  97. Marcus Bednara, Jürgen Teich
    Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2003, v:26, n:2, pp:149-165 [Journal]
  98. Jürgen Teich, Sándor P. Fekete, Jörg Schepers
    Optimization of Dynamic Hardware Reconfigurations. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2001, v:19, n:1, pp:57-75 [Journal]
  99. Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich
    Interactive presentation: Reliability-aware system synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:409-414 [Conf]
  100. Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich
    Minimizing Communication Cost for Reconfigurable Slot Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  101. Daniel Ziener, Stefan Assmus, Jürgen Teich
    Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  102. Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich
    Modeling and Synthesis of Hardware-Software Morphing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2746-2749 [Conf]
  103. Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
    Massively Parallel Processor Architectures: A Co-design Approach. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:61-68 [Conf]
  104. Joachim Keinert, Christian Haubelt, Jürgen Teich
    Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:161-168 [Conf]
  105. Thilo Streichert, Christian Haubelt, Jürgen Teich
    Multi-Objective Topology Optimization for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:93-98 [Conf]
  106. Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
    Solving Multi-objective Pseudo-Boolean Problems. [Citation Graph (0, 0)][DBLP]
    SAT, 2007, pp:56-69 [Conf]
  107. S. Helwig, Christian Haubelt, Jürgen Teich
    Modeling and analysis of indirect communication in particle swarm optimization. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:1246-1253 [Conf]
  108. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices [Citation Graph (0, 0)][DBLP]
    CoRR, 2005, v:0, n:, pp:- [Journal]
  109. Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:143-0 [Journal]
  110. Jürgen Teich
    Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:139-0 [Journal]
  111. Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich
    Design space exploration of reliable networked embedded systems. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:751-763 [Journal]
  112. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
    Efficient control generation for mapping nested loop programs onto processor arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:300-309 [Journal]
  113. Eckart Zitzler, Jürgen Teich, S. S. Bhattclcharyya
    Evolutionary algorithms for the synthesis of embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:452-455 [Journal]
  114. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState-an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:524-544 [Journal]
  115. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich
    SPI - a system model for heterogeneously specified embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:379-389 [Journal]
  116. Jürgen Teich, Shuvra S. Bhattacharyya
    Analysis of Dataflow Programs with Interval-limited Data-rates. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:247-258 [Journal]
  117. Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda
    The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:15-31 [Journal]

  118. Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. [Citation Graph (, )][DBLP]


  119. Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. [Citation Graph (, )][DBLP]


  120. Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication. [Citation Graph (, )][DBLP]


  121. Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. [Citation Graph (, )][DBLP]


  122. Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. [Citation Graph (, )][DBLP]


  123. Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. [Citation Graph (, )][DBLP]


  124. Impact of Loop Tiling on the Controller Logic of Acceleration Engines. [Citation Graph (, )][DBLP]


  125. Efficient symbolic multi-objective design space exploration. [Citation Graph (, )][DBLP]


  126. Concepts for Autonomous Control Flow Checking for Embedded CPUs. [Citation Graph (, )][DBLP]


  127. Symbolic voter placement for dependability-aware system synthesis. [Citation Graph (, )][DBLP]


  128. FlexRay schedule optimization of the static segment. [Citation Graph (, )][DBLP]


  129. Exploiting data-redundancy in reliability-aware networked embedded system design. [Citation Graph (, )][DBLP]


  130. Concurrent topology and routing optimization in automotive network integration. [Citation Graph (, )][DBLP]


  131. Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. [Citation Graph (, )][DBLP]


  132. Towards scalable system-level reliability analysis. [Citation Graph (, )][DBLP]


  133. 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  134. 06141 Executive Summary -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  135. Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. [Citation Graph (, )][DBLP]


  136. Symbolic Reliability Analysis and Optimization of ECU Networks. [Citation Graph (, )][DBLP]


  137. CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. [Citation Graph (, )][DBLP]


  138. Incorporating graceful degradation into embedded system design. [Citation Graph (, )][DBLP]


  139. Combined system synthesis and communication architecture exploration for MPSoCs. [Citation Graph (, )][DBLP]


  140. Model-based synthesis and optimization of static multi-rate image processing algorithms. [Citation Graph (, )][DBLP]


  141. Efficient High-Level modeling in the networking domain. [Citation Graph (, )][DBLP]


  142. Robust design of embedded systems. [Citation Graph (, )][DBLP]


  143. A rapid prototyping system for error-resilient multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  144. Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. [Citation Graph (, )][DBLP]


  145. Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]


  146. A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. [Citation Graph (, )][DBLP]


  147. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. [Citation Graph (, )][DBLP]


  148. Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. [Citation Graph (, )][DBLP]


  149. Efficient Reconfigurable On-Chip Buses for FPGAs. [Citation Graph (, )][DBLP]


  150. Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]


  151. Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. [Citation Graph (, )][DBLP]


  152. Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. [Citation Graph (, )][DBLP]


  153. A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. [Citation Graph (, )][DBLP]


  154. No-break dynamic defragmentation of reconfigurable devices. [Citation Graph (, )][DBLP]


  155. A comparison of embedded reconfigurable video-processing architectures. [Citation Graph (, )][DBLP]


  156. Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. [Citation Graph (, )][DBLP]


  157. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]


  158. ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. [Citation Graph (, )][DBLP]


  159. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  160. General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. [Citation Graph (, )][DBLP]


  161. Self-organizing multi-cue fusion for FPGA-based embedded imaging. [Citation Graph (, )][DBLP]


  162. A Sequential Learning Resource Allocation Network for Image Processing Applications. [Citation Graph (, )][DBLP]


  163. System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. [Citation Graph (, )][DBLP]


  164. Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads. [Citation Graph (, )][DBLP]


  165. Classification of General Data Flow Actors into Known Models of Computation. [Citation Graph (, )][DBLP]


  166. Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  167. A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. [Citation Graph (, )][DBLP]


  168. 3D Person Tracking with a Color-Based Particle Filter. [Citation Graph (, )][DBLP]


  169. Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. [Citation Graph (, )][DBLP]


  170. Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. [Citation Graph (, )][DBLP]


  171. Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. [Citation Graph (, )][DBLP]


  172. Multi-objective routing and topology optimization in networked embedded systems. [Citation Graph (, )][DBLP]


  173. Efficient event-driven simulation of parallel processor architectures. [Citation Graph (, )][DBLP]


  174. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. [Citation Graph (, )][DBLP]


  175. Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. [Citation Graph (, )][DBLP]


  176. Self-organizing Bandwidth Sharing in Priority-Based Medium Access. [Citation Graph (, )][DBLP]


  177. SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. [Citation Graph (, )][DBLP]


  178. A feasibility-preserving local search operator for constrained discrete optimization problems. [Citation Graph (, )][DBLP]


  179. Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. [Citation Graph (, )][DBLP]


  180. Mapping Actor-Oriented Models to TLM Architectures. [Citation Graph (, )][DBLP]


  181. Efficient Representation and Simulation of Model-Based Designs. [Citation Graph (, )][DBLP]


  182. Defragmenting the Module Layout of a Partially Reconfigurable Device [Citation Graph (, )][DBLP]


  183. DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices [Citation Graph (, )][DBLP]


  184. Maintaining Virtual Areas on FPGAs using Strip Packing with Delays [Citation Graph (, )][DBLP]


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