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Marius Grannæs:
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- Haakon Dybdahl, Marius Grannæs, Lasse Natvig
Cache Write-Back Schemes for Embedded Destructive-Read DRAM. [Citation Graph (0, 0)][DBLP] ARCS, 2006, pp:145-159 [Conf]
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. [Citation Graph (, )][DBLP]
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. [Citation Graph (, )][DBLP]
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. [Citation Graph (, )][DBLP]
Low-cost open-page prefetch scheduling in chip multiprocessors. [Citation Graph (, )][DBLP]
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