The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ali Ahmadinia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ali Ahmadinia, Christophe Bobda, Jürgen Teich
    A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS, 2004, pp:125-139 [Conf]
  2. Christophe Bobda, Ali Ahmadinia, Jürgen Teich
    Generation of Distributed Arithmetic Designs for Reconfigurable Application. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:205-214 [Conf]
  3. Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru
    Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:61-66 [Conf]
  4. Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich
    A Flexible Reconfiguration Manager for the Erlangen Slot Machine. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:183-194 [Conf]
  5. Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
    Defragmenting the Module Layout of a Partially Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:92-104 [Conf]
  6. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:319-320 [Conf]
  7. Ali Ahmadinia
    Optimization Algorithms for Dynamic Reconfigurable Embedded Systems p. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1168- [Conf]
  8. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:847-851 [Conf]
  9. Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:153-158 [Conf]
  10. Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
    A Dynamic NoC Approach for Communication in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1032-1036 [Conf]
  11. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
    The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:37-42 [Conf]
  12. Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
    A New Approach for On-line Placement on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  13. Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
    Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  14. Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
    Packet Routing in Dynamically Changing Networks on Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  15. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:84-90 [Conf]
  16. Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
    Task scheduling for heterogeneous reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:22-27 [Conf]
  17. Ali Ahmadinia, Jürgen Teich
    Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:118-122 [Conf]
  18. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices [Citation Graph (0, 0)][DBLP]
    CoRR, 2004, v:0, n:, pp:- [Journal]
  19. Christophe Bobda, Ali Ahmadinia
    Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:443-451 [Journal]
  20. Ali Ahmadinia
    Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:673-680 [Journal]
  21. Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan
    Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1875-1878 [Conf]
  22. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices [Citation Graph (0, 0)][DBLP]
    CoRR, 2005, v:0, n:, pp:- [Journal]
  23. Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda
    The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:15-31 [Journal]

  24. Adaptive Router Architecture for Optimising Quality of Service in Networks-on-Chip. [Citation Graph (, )][DBLP]


  25. SystemC-based Custom Reconfigurable Cores for Wireless Applications. [Citation Graph (, )][DBLP]


  26. System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. [Citation Graph (, )][DBLP]


  27. Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications. [Citation Graph (, )][DBLP]


  28. Efficient High-Level Power Estimation for Multi-standard Wireless Systems. [Citation Graph (, )][DBLP]


  29. Optimization of Reconfigurable Multi-core SOCs for Multi-standard Applications. [Citation Graph (, )][DBLP]


  30. Machine Vision Application to Automatic Intruder Detection Using CCTV. [Citation Graph (, )][DBLP]


  31. System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design. [Citation Graph (, )][DBLP]


  32. Hybrid Communication Medium for Adaptive SoC Architectures. [Citation Graph (, )][DBLP]


  33. Defragmenting the Module Layout of a Partially Reconfigurable Device [Citation Graph (, )][DBLP]


  34. DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002