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Christophe Bobda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ali Ahmadinia, Christophe Bobda, Jürgen Teich
    A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS, 2004, pp:125-139 [Conf]
  2. Christophe Bobda, Ali Ahmadinia, Jürgen Teich
    Generation of Distributed Arithmetic Designs for Reconfigurable Application. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:205-214 [Conf]
  3. Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru
    Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:61-66 [Conf]
  4. Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich
    A Flexible Reconfiguration Manager for the Erlangen Slot Machine. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:183-194 [Conf]
  5. Achim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann
    A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11130-11131 [Conf]
  6. Klaus Danne, Christophe Bobda, Heiko Kalte
    Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:147-153 [Conf]
  7. Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
    Defragmenting the Module Layout of a Partially Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:92-104 [Conf]
  8. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:319-320 [Conf]
  9. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:847-851 [Conf]
  10. Brandon Blodget, Christophe Bobda, Michael Hübner, Adronis Niyonkuru
    Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:801-810 [Conf]
  11. Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:153-158 [Conf]
  12. Christophe Bobda, Klaus Danne, André Linarth
    Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1123-1126 [Conf]
  13. Christophe Bobda, Thomas Lehmann
    Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:759-768 [Conf]
  14. Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
    A Dynamic NoC Approach for Communication in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1032-1036 [Conf]
  15. Klaus Danne, Christophe Bobda, Heiko Kalte
    Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:272-281 [Conf]
  16. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
    The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:37-42 [Conf]
  17. Christophe Bobda
    Temporal Partitioning and Sequencing of Dataflow Graphs on Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2002, pp:185-194 [Conf]
  18. Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
    A New Approach for On-line Placement on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  19. Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
    Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  20. Klaus Danne, Christophe Bobda
    Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-Off Analysis. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  21. Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
    Packet Routing in Dynamically Changing Networks on Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  22. Tertulien Ndjountche, Fa-Long Luo, Christophe Bobda
    A CMOS front-end architecture for hard-disk drive read-channel equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2184-2187 [Conf]
  23. Christophe Bobda
    Building Up a Course in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:7-8 [Conf]
  24. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:84-90 [Conf]
  25. Christophe Bobda, Nils Steenbock
    Singular Value Decomposition on Distributed Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:38-43 [Conf]
  26. Christophe Bobda, Nils Steenbock
    A Rapid Prototyping Environment for Distributed Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:153-158 [Conf]
  27. Felix Mühlbauer, Christophe Bobda
    Design and Implementation of an Object Tracker on a Reconfigurable System on Chip. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:230- [Conf]
  28. Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Christophe Bobda
    A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:71-77 [Conf]
  29. Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
    Task scheduling for heterogeneous reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:22-27 [Conf]
  30. Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
    Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices [Citation Graph (0, 0)][DBLP]
    CoRR, 2004, v:0, n:, pp:- [Journal]
  31. Christophe Bobda, Ali Ahmadinia
    Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:443-451 [Journal]
  32. Thomas Haller, José Rodrigo Azambuja, Christophe Bobda
    Automatic Generation of Adaptive Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:192-193 [Conf]
  33. S. Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber
    A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:98-105 [Conf]
  34. Thomas Haller, Christophe Bobda
    Adaptive Network for Multiprocessing in Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:106-110 [Conf]
  35. Lars Middendorf, Felix Mühlbauer, Georg Umlauf, Christophe Bobda
    Embedded Vertex Shader in FPGA. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:155-164 [Conf]
  36. Dominik Murr, Felix Mühlbauer, Falko Dressler, Christophe Bobda
    Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:373-386 [Conf]
  37. Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
    A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices [Citation Graph (0, 0)][DBLP]
    CoRR, 2005, v:0, n:, pp:- [Journal]
  38. Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda
    The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:15-31 [Journal]

  39. Hardware/Software co-design of a key point detector on FPGA. [Citation Graph (, )][DBLP]


  40. CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  41. SoPC architecture for a Key Point Detector. [Citation Graph (, )][DBLP]


  42. A new deadlock-free fault-tolerant routing algorithm for NoC interconnections. [Citation Graph (, )][DBLP]


  43. Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs. [Citation Graph (, )][DBLP]


  44. Design of adaptive multiprocessor on chip systems. [Citation Graph (, )][DBLP]


  45. Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling. [Citation Graph (, )][DBLP]


  46. SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips. [Citation Graph (, )][DBLP]


  47. Application-driven architecture synthesis of on-chip Multiprocessor systems. [Citation Graph (, )][DBLP]


  48. Defragmenting the Module Layout of a Partially Reconfigurable Device [Citation Graph (, )][DBLP]


  49. DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices [Citation Graph (, )][DBLP]


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