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Erik Maehle :
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Carsten Albrecht , Rainer Hagenau , Erik Maehle , Andreas Döring , Andreas Herkersdorf A Comparison of Parallel Programming Models of Network Processors. [Citation Graph (0, 0)][DBLP ] ARCS Workshops, 2004, pp:390-399 [Conf ] Chr. Roßmanith , O. Huwendiek , Heinz Handels , Werner Brockmann , A. Hager , H. Laqua , Erik Maehle , Siegfried J. Pöppl Analyse von Augenhintergrundbildern zur Bewertung des Erfolges von Operationen an der Macula pucker. [Citation Graph (0, 0)][DBLP ] Bildverarbeitung für die Medizin, 1998, pp:- [Conf ] Andreas Bauch , Thomas Kosch , Erik Maehle , Wolfgang Obelöer The Software-Monitor DELTA-T and Its Use for Performance Measurements of Some Farming Variants on the Multi-Transputer System DAMP. [Citation Graph (0, 0)][DBLP ] CONPAR, 1992, pp:67-78 [Conf ] Erik Maehle , Klaus Moritzen , Klaus Wirl Fault-Tolerant Hardware Configuration Management on the Multiprocessor System DIRMU 25. [Citation Graph (0, 0)][DBLP ] CONPAR, 1986, pp:190-197 [Conf ] Johann Rost , Erik Maehle A Distributed Algorithm for Dynamic Task Scheduling. [Citation Graph (0, 0)][DBLP ] CONPAR, 1990, pp:628-639 [Conf ] Dieter Jäpel , Erik Maehle , Klaus Wirl Einsatz des DIRMU-Multiprozessorsystems in der Mustererkennung. [Citation Graph (0, 0)][DBLP ] DAGM-Symposium, 1985, pp:185-190 [Conf ] Andreas Herkersdorf , L. Heusler , Erik Maehle Route Discovery in Multistage Switch Fabrics. [Citation Graph (0, 0)][DBLP ] Data Communication Networks and their Performance, 1993, pp:103-118 [Conf ] Bernd Bieker , Erik Maehle , Geert Deconinck , Johan Vounckx Reconfiguration and Checkpointing in Massively Parallel Systems. [Citation Graph (0, 0)][DBLP ] EDCC, 1994, pp:353-370 [Conf ] Andreas Bauch , Reinhold Braam , Erik Maehle DAMP - A Dynamic Reconfigurable Multiprocessor System with a Distributed Switching Network. [Citation Graph (0, 0)][DBLP ] EDMCC, 1991, pp:495-504 [Conf ] Florian Mösch , Marek Litza , Adam El Sayed Auf , Erik Maehle , Karl-Erwin Großpietsch , Werner Brockmann ORCA - Towards an Organic Robotic Control Architecture. [Citation Graph (0, 0)][DBLP ] IWSOS/EuroNGI, 2006, pp:251-253 [Conf ] Erik Maehle , Shi-Cheng Hu Ein Baukastenkonzept für fehlertolerante Multi-Mikroprozessorsysteme. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung, 1981, pp:307-316 [Conf ] Andreas Bauch , Erik Maehle Self-Diagnosis, Reconfiguration and Recovery in the Dynamical Reconfigurable Multiprocessor Systemn DAMP. [Citation Graph (0, 0)][DBLP ] Fault-Tolerant Computing Systems, 1991, pp:18-29 [Conf ] Erik Maehle , Hans Joseph Selbstdiagnose in fehlertoleranten Dirmu-Multimikroprozessorkonfigurationen. [Citation Graph (0, 0)][DBLP ] Fehlertolerierende Rechensysteme, 1982, pp:59-73 [Conf ] Erik Maehle , Klaus Moritzen , Klaus Wirl Experimente mit N-Version Programming auf dem DIRMU Multiprozessorsystem. [Citation Graph (0, 0)][DBLP ] Software-Fehlertoleranz und -Zuverlässigkeit, 1984, pp:133-142 [Conf ] Wolfgang Händler , Erik Maehle , Klaus Wirl Dirmu Multiprocessor Configurations. [Citation Graph (0, 0)][DBLP ] ICPP, 1985, pp:652-656 [Conf ] Andreas Döring , Wolfgang Obelöer , Gunther Lustig , Erik Maehle A Flexible Approach for a Fault-Tolerant Router. [Citation Graph (0, 0)][DBLP ] IPPS/SPDP Workshops, 1998, pp:693-713 [Conf ] Roman Koch , Thilo Pionteck , Carsten Albrecht , Erik Maehle An adaptive system-on-chip for network applications. [Citation Graph (0, 0)][DBLP ] IPDPS, 2006, pp:- [Conf ] Erik Maehle Entwurf von Selbsttestprogrammen für Mikrocomputer. [Citation Graph (0, 0)][DBLP ] Microcomputing, 1979, pp:204-216 [Conf ] Carsten Albrecht , Jürgen Foag , Roman Koch , Erik Maehle DynaCORE - A Dynamically Reconfigurable Coprocessor Architecture for Network Processors. [Citation Graph (0, 0)][DBLP ] PDP, 2006, pp:101-108 [Conf ] Werner Brockmann , Thomas Kosch , Erik Maehle Rule-Based Routing in Massively Parallel Systems. [Citation Graph (0, 0)][DBLP ] PDP, 1996, pp:154-161 [Conf ] Karl-Erwin Großpietsch , Erik Maehle Routing to Support Communication in Dependable Networks. [Citation Graph (0, 0)][DBLP ] PDP, 2002, pp:71-0 [Conf ] Konstantin Trachos , Erik Maehle A class hierarchy emulating virtual shared objects on message-passing systems. [Citation Graph (0, 0)][DBLP ] PDP, 1995, pp:174-181 [Conf ] Andreas Döring , Wolfgang Obelöer , Gunther Lustig , Erik Maehle Low-Level SCI Protocols and Their Application to Flexible Switches. [Citation Graph (0, 0)][DBLP ] Scalable Coherent Interface, 1999, pp:105-123 [Conf ] Peter Arbenz , Helmar Burkhart , Erik Maehle , Olaf Schenk Special section: SPEEDUP Workshop on Modern algorithms in computational science and information technology. [Citation Graph (0, 0)][DBLP ] Future Generation Comp. Syst., 2005, v:21, n:8, pp:1249-1250 [Journal ] Elmar Dilger , Erik Maehle Systemarchitektur und Fehlertoleranz. [Citation Graph (0, 0)][DBLP ] Informatik Spektrum, 1986, v:9, n:2, pp:110-118 [Journal ] Karl-Erwin Großpietsch , Erik Maehle Fehlerbehandlung in komplexen nebenläufigen Systemen. [Citation Graph (0, 0)][DBLP ] Informatik Spektrum, 1998, v:21, n:6, pp:347-355 [Journal ] Rainer Hagenau , Carsten Albrecht , Erik Maehle , Andreas Döring Parallel Processing in Network Processor Architectures (Parallelverarbeitung in Netzwerkprozessorarchitekturen). [Citation Graph (0, 0)][DBLP ] it - Information Technology, 2005, v:47, n:3, pp:123-131 [Journal ] Werner Brockmann , Wolfgang Heide , Ralf Kluthe , Detlef Kömpf , Erik Maehle , Andreas Sprenger Modellierung der kortikalen Steuerung von Blicksakkaden bei der visuellen Exploration. [Citation Graph (0, 0)][DBLP ] KI, 1999, v:13, n:1, pp:36-38 [Journal ] Andreas Herkersdorf , L. Heusler , Erik Maehle Route Discovery for Multistage Fabrics in ATM Switching Nodes. [Citation Graph (0, 0)][DBLP ] Perform. Eval., 1995, v:22, n:3, pp:221-238 [Journal ] Thilo Pionteck , Carsten Albrecht , Roman Koch , Erik Maehle , Michael Hübner , Jürgen Becker Communication Architectures for Dynamically Reconfigurable FPGA Designs. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-8 [Conf ] Roman Koch , Thilo Pionteck , Carsten Albrecht , Erik Maehle A Lightweight Framework for Runtime Reconfigurable System Prototyping. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2007, pp:61-64 [Conf ] Ein Organic Computing Ansatz zur Steuerung einer sechsbeinigen Laufmaschine. [Citation Graph (, )][DBLP ] Firefly Flashing Synchronization as Inspiration for Self-synchronization of Walking Robot Gait Patterns Using a Decentralized Robot Control Architecture. [Citation Graph (, )][DBLP ] Artificial Immune System Based Robot Anomaly Detection Engine for Fault Tolerant Robots. [Citation Graph (, )][DBLP ] Design and Simulation of Runtime Reconfigurable Systems. [Citation Graph (, )][DBLP ] Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor. [Citation Graph (, )][DBLP ] On the design parameters of runtime reconfigurable systems. [Citation Graph (, )][DBLP ] Network processors. [Citation Graph (, )][DBLP ] Designing coprocessors for hybrid compute systems. [Citation Graph (, )][DBLP ] Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. [Citation Graph (, )][DBLP ] WCET determination tool for embedded systems software. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.306secs