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Andreas Herkersdorf: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Carsten Albrecht, Rainer Hagenau, Erik Maehle, Andreas Döring, Andreas Herkersdorf
    A Comparison of Parallel Programming Models of Network Processors. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:390-399 [Conf]
  2. Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
    Towards a Framework and a Design Methodology for Autonomous SoC. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:101-108 [Conf]
  3. Walter Stechele, Stephan Herrmann, Andreas Herkersdorf
    Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:225-234 [Conf]
  4. Faisal Suleman, Dirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf
    Adaptable DSP Functions for Dynamically Reconfigurable Communication Systems. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:19-26 [Conf]
  5. Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild
    FlexPath NP: a network processor concept with application-driven flexible processing paths. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:279-284 [Conf]
  6. Andreas Herkersdorf, Walter Stechele
    AutoVision: flexible processor architecture for video-assisted driving. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:556- [Conf]
  7. Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
    Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:248-253 [Conf]
  8. Paul Zuber, Armin Windschiegl, Raúl Medina Beltán de Otálora, Walter Stechele, Andreas Herkersdorf
    Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:986-987 [Conf]
  9. Andreas Herkersdorf, L. Heusler, Erik Maehle
    Route Discovery in Multistage Switch Fabrics. [Citation Graph (0, 0)][DBLP]
    Data Communication Networks and their Performance, 1993, pp:103-118 [Conf]
  10. Dirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf
    Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:312-315 [Conf]
  11. Andreas Herkersdorf, Wolfgang Rosenstiel
    Towards a Framework and a Design Methodology for Autonomic Integrated Systems. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2004, pp:610-615 [Conf]
  12. Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
    An Architecture for Runtime Evaluation of SoC Reliability. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2006, pp:177-0 [Conf]
  13. Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
    Towards a Framework and a Design Methodology for Autonomic SoC. [Citation Graph (0, 0)][DBLP]
    ICAC, 2005, pp:391-392 [Conf]
  14. Willibald A. Doeringer, Douglas Dykeman, Antonius P. J. Engbersen, Roch Guérin, Andreas Herkersdorf, L. Heusler
    Fast Connection Establishment in Large-Scale Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1993, pp:489-496 [Conf]
  15. Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
    A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:259-264 [Conf]
  16. Samarjit Chakraborty, Simon Künzli, Lothar Thiele, Andreas Herkersdorf, Patricia Sagmeister
    Performance evaluation of network processor architectures: combining simulation with analytical estimation. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:41, n:5, pp:641-665 [Journal]
  17. Maria Gabrani, Gero Dittmann, Andreas Döring, Andreas Herkersdorf, Patricia Sagmeister, Jan van Lunteren
    Design methodology for a modular service-driven network processor architecture. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:41, n:5, pp:623-640 [Journal]
  18. Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb
    Design Methodology for a Large Communication Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:86-94 [Journal]
  19. James R. Allen Jr., Brian M. Bass, Claude Basso, Richard H. Boivie, Jean Calvignac, Gordon T. Davis, Laurent Freléchoux, Marco Heddes, Andreas Herkersdorf, Andreas Kind, Joe F. Logan, Mohammad Peyravian, Mark A. Rinaldi, Ravi K. Sabhikhi, Michael S. Siegel, Marcel Waldvogel
    IBM PowerNP network processor: Hardware, software, and applications. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:177-194 [Journal]
  20. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  21. Andreas Herkersdorf, L. Heusler, Erik Maehle
    Route Discovery for Multistage Fabrics in ATM Switching Nodes. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 1995, v:22, n:3, pp:221-238 [Journal]
  22. David E. Taylor, Andreas Herkersdorf, Andreas Döring, Gero Dittmann
    Robust header compression (ROHC) in next-generation network processors. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2005, v:13, n:4, pp:755-768 [Journal]
  23. Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
    Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:152-159 [Conf]
  24. Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
    Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:338-341 [Conf]
  25. Christopher Claus, Walter Stechele, Andreas Herkersdorf
    Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:181-0 [Journal]
  26. Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
    Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:703-718 [Journal]

  27. A Hardware Packet Re-Sequencer Unit for Network Processors. [Citation Graph (, )][DBLP]


  28. Autonomic Workload Management for Multi-core Processor Systems. [Citation Graph (, )][DBLP]


  29. A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces. [Citation Graph (, )][DBLP]


  30. Buffer allocation for advanced packet segmentation in Network Processors. [Citation Graph (, )][DBLP]


  31. SysCOLA: a framework for co-development of automotive software and system platform. [Citation Graph (, )][DBLP]


  32. An efficient approach for system-level timing simulation of compiler-optimized embedded software. [Citation Graph (, )][DBLP]


  33. Reconfigurable Processing Units vs. Reconfigurable Interconnects. [Citation Graph (, )][DBLP]


  34. Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. [Citation Graph (, )][DBLP]


  35. A rapid prototyping system for error-resilient multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  36. An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. [Citation Graph (, )][DBLP]


  37. Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. [Citation Graph (, )][DBLP]


  38. Network processors. [Citation Graph (, )][DBLP]


  39. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  40. Learning Classifier Tables for Autonomic Systems on Chip. [Citation Graph (, )][DBLP]


  41. Workshop "Adaptive and Organic Systems". [Citation Graph (, )][DBLP]


  42. An Application-Aware Load Balancing Strategy for Network Processors. [Citation Graph (, )][DBLP]


  43. A Simulation Approach for Performance Validation during Embedded Systems Design. [Citation Graph (, )][DBLP]


  44. Flow Analysis on Intermediate Source Code for WCET Estimation of Compiler-Optimized Programs. [Citation Graph (, )][DBLP]


  45. Improving memory subsystem performance in network processors with smart packet segmentation. [Citation Graph (, )][DBLP]


  46. SciSim: a software performance estimation framework using source code instrumentation. [Citation Graph (, )][DBLP]


  47. Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. [Citation Graph (, )][DBLP]


  48. Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. [Citation Graph (, )][DBLP]


  49. A Model Driven Development Approach for Implementing Reactive Systems in Hardware. [Citation Graph (, )][DBLP]


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