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Hans-Joachim Wunderlich: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Talal Arnaout, Peter Göhner, Hans-Joachim Wunderlich, Eduard Zimmer
    Reliability Considerations forMechatronic Systems on the Basis of a State Model. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:106-112 [Conf]
  2. Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich
    Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:492-499 [Conf]
  3. Bernhard Eschermann, Hans-Joachim Wunderlich
    A Unified Approach for the Synthesis of Self-Testable Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:372-377 [Conf]
  4. Hans-Joachim Wunderlich
    On Computing Optimized Input Probabilities for Random Tests. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:392-398 [Conf]
  5. Hans-Joachim Wunderlich, Wolfgang Rosenstiel
    On fault modeling for dynamic MOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:540-546 [Conf]
  6. Hans-Joachim Wunderlich
    PROTEST: a tool for probabilistic testability analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:204-211 [Conf]
  7. Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
    Optimal Hardware Pattern Generation for Functional BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:292-297 [Conf]
  8. Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
    On applying the set covering model to reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:156-161 [Conf]
  9. Rainer Dorsch, Hans-Joachim Wunderlich
    Using mission logic for embedded testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:805- [Conf]
  10. Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik
    Symmetric Transparent BIST for RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:702-707 [Conf]
  11. A. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich
    Circuit partitioning for efficient logic BIST synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:86-91 [Conf]
  12. Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich
    Impact of Test Point Insertion on Silicon Area and Timing during Layout. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:810-815 [Conf]
  13. Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich
    Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:173-179 [Conf]
  14. Jun Zhou, Hans-Joachim Wunderlich
    Software-based self-test of processors under power constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:430-435 [Conf]
  15. Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
    Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:185-190 [Conf]
  16. Talal Arnaout, Gunter Bartsch, Hans-Joachim Wunderlich
    Some Common Aspects of Design Validation, Debug and Diagnosis. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:3-10 [Conf]
  17. Marie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich
    Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:135-139 [Conf]
  18. Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich
    Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:339-350 [Conf]
  19. Sybille Hellebrand, Hans-Joachim Wunderlich
    Synthesis of Self-Testable Controllers. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:580-585 [Conf]
  20. Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich
    On the Reliability Evaluation of SRAM-Based FPGA Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:403-408 [Conf]
  21. Albrecht P. Stroele, Hans-Joachim Wunderlich
    Signature Analysis and Test Scheduling for Self-Testable Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:96-103 [Conf]
  22. Sybille Hellebrand, Hans-Joachim Wunderlich
    Automatisierung des Entwurfs vollständig testbarer Schaltungen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:145-159 [Conf]
  23. Jun Zhou, Hans-Joachim Wunderlich
    Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:441- [Conf]
  24. Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
    Synthesis of irregular combinational functions with large don't care sets. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:287-292 [Conf]
  25. Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich
    Pattern generation for a deterministic BIST scheme. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:88-94 [Conf]
  26. Sybille Hellebrand, Hans-Joachim Wunderlich
    An efficient procedure for the synthesis of fast self-testable controller structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:110-116 [Conf]
  27. Albrecht P. Stroele, Hans-Joachim Wunderlich
    Test register insertion with minimum hardware cost. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:95-101 [Conf]
  28. Hans-Joachim Wunderlich, Gundolf Kiefer
    Bit-flipping BIST. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:337-343 [Conf]
  29. Bernhard Eschermann, Hans-Joachim Wunderlich
    Emulation of Scan Paths in Sequential Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:136-147 [Conf]
  30. Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rainer Dorsch, Hans-Joachim Wunderlich
    Development of an audio player as system-on-a-chip using an open source platform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2935-2938 [Conf]
  31. Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
    Non-intrusive BIST for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:644-651 [Conf]
  32. Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer
    Adapting an SoC to ATE Concurrent Test Capabilities. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1169-1175 [Conf]
  33. Rainer Dorsch, Hans-Joachim Wunderlich
    Tailoring ATPG for embedded testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:530-537 [Conf]
  34. Rainer Dorsch, Hans-Joachim Wunderlich
    Accumulator based deterministic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:412-421 [Conf]
  35. Stefan Gerstendorfer, Hans-Joachim Wunderlich
    Minimized power consumption for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:77-84 [Conf]
  36. Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
    Efficient Pattern Mapping for Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:48-56 [Conf]
  37. Sybille Hellebrand, Hans-Joachim Wunderlich
    The Pseudo-Exhaustive Test of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:19-27 [Conf]
  38. Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
    Mixed-Mode BIST Using Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:195-204 [Conf]
  39. Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang
    A mixed mode BIST scheme based on reseeding of folding counters. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:778-784 [Conf]
  40. Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich
    Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:461-469 [Conf]
  41. Gundolf Kiefer, Hans-Joachim Wunderlich
    Using BIST Control for Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:347-355 [Conf]
  42. Gundolf Kiefer, Hans-Joachim Wunderlich
    Deterministic BIST with multiple scan chains. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1057-1064 [Conf]
  43. Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
    Application of deterministic logic BIST on industrial circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:105-114 [Conf]
  44. Thomas Kropf, Hans-Joachim Wunderlich
    A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:57-66 [Conf]
  45. Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
    Two-dimensional test data compression for scan-based deterministic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:894-902 [Conf]
  46. Olaf Stern, Hans-Joachim Wunderlich
    Simulation Results of an Efficient Defect-Analysis Procedure. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:729-738 [Conf]
  47. Albrecht P. Stroele, Hans-Joachim Wunderlich
    Configuring Flip-Flops to BIST Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:939-948 [Conf]
  48. Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
    X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:442-451 [Conf]
  49. Hans-Joachim Wunderlich
    Multiple Distributions for Biased Random Test Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:236-244 [Conf]
  50. Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden
    Test Engineering Education in Europe: the EuNICE-Test Project. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:85-86 [Conf]
  51. Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
    Power Dissipation During Testing: Should We Worry About it? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:456-457 [Conf]
  52. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
    A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:306-311 [Conf]
  53. Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel
    Implementing a Scheme for External Deterministic Self-Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:101-106 [Conf]
  54. Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
    Error Detecting Refreshment for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:384-390 [Conf]
  55. Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich
    Fast Self-Recovering Controllers. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:296-302 [Conf]
  56. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
    High Defect Coverage with Low-Power Test Sequences in a BIST Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:44-52 [Journal]
  57. Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
    Synthesizing Fast, Online-Testable Control Units. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:36-41 [Journal]
  58. Hans-Joachim Wunderlich, Sandeep K. Shukla
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:65-66 [Journal]
  59. Hans-Joachim Wunderlich, Michael H. Schulz
    Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1992, v:15, n:1, pp:23-32 [Journal]
  60. Hans-Joachim Wunderlich
    BIST for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:55-78 [Journal]
  61. Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
    A Mixed-Mode BIST Scheme Based on Folding Compression. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:2, pp:203-212 [Journal]
  62. Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
    Efficient Online and Offline Testing of Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:7, pp:801-809 [Journal]
  63. Bernhard Eschermann, Hans-Joachim Wunderlich
    Optimized synthesis techniques for testable sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:301-312 [Journal]
  64. Albrecht P. Stroele, Hans-Joachim Wunderlich
    Hardware-optimal test register insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:531-539 [Journal]
  65. Hans-Joachim Wunderlich
    Multiple distributions for biased random test patterns. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:6, pp:584-593 [Journal]
  66. Hans-Joachim Wunderlich, Sybille Hellebrand
    The pseudoexhaustive test of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:26-33 [Journal]
  67. Shishpal Rawat, Hans-Joachim Wunderlich
    Introduction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:397-398 [Journal]
  68. Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
    X-masking during logic BIST and its impact on defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:193-202 [Journal]
  69. Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
    Scan Test Planning for Power Reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:521-526 [Conf]
  70. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
    Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:403-408 [Conf]
  71. Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
    Deterministic Logic BIST for Transition Fault Testing. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:123-130 [Conf]
  72. Stefan Holst, Hans-Joachim Wunderlich
    Adaptive Debug and Diagnosis without Fault Dictionaries. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:7-12 [Conf]
  73. Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
    An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:91-96 [Conf]
  74. Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
    DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2006, v:48, n:5, pp:304-0 [Journal]

  75. Scan chain clustering for test power reduction. [Citation Graph (, )][DBLP]


  76. Efficient fault simulation on many-core processors. [Citation Graph (, )][DBLP]


  77. Scan Chain Organization for Embedded Diagnosis. [Citation Graph (, )][DBLP]


  78. Fast controllers for data dominated applications. [Citation Graph (, )][DBLP]


  79. Test exploration and validation using transaction level models. [Citation Graph (, )][DBLP]


  80. A diagnosis algorithm for extreme space compaction. [Citation Graph (, )][DBLP]


  81. BISD: Scan-based Built-In self-diagnosis. [Citation Graph (, )][DBLP]


  82. Test Set Stripping Limiting the Maximum Number of Specified Bits. [Citation Graph (, )][DBLP]


  83. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. [Citation Graph (, )][DBLP]


  84. Software-Based Hardware Fault Tolerance for Many-Core Architectures. [Citation Graph (, )][DBLP]


  85. The effectiveness of different test sets for PLAs. [Citation Graph (, )][DBLP]


  86. Tools and devices supporting the pseudo-exhaustive test. [Citation Graph (, )][DBLP]


  87. Integrating Scan Design and Soft Error Correction in Low-Power Applications. [Citation Graph (, )][DBLP]


  88. Signature Rollback - A Technique for Testing Robust Circuits. [Citation Graph (, )][DBLP]


  89. Algorithm-based fault tolerance for many-core architectures. [Citation Graph (, )][DBLP]


  90. Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. [Citation Graph (, )][DBLP]


  91. Test Encoding for Extreme Response Compaction. [Citation Graph (, )][DBLP]


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