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Samy Meftali: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser
    Estimating Energy Consumption for an MPSoC Architectural Exploration. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:298-310 [Conf]
  2. Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
    Massively parallel processing on a chip. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:277-286 [Conf]
  3. Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic generation of embedded memory wrapper for multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:596-601 [Conf]
  4. Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:193-204 [Conf]
  5. Samy Meftali, Jean-Luc Dekeyser
    SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. [Citation Graph (0, 0)][DBLP]
    Virtual Enterprises and Collaborative Networks, 2004, pp:387-394 [Conf]
  6. Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli
    Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:26-31 [Conf]
  7. Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    An optimal memory allocation for application-specific multiprocessor system-on-chip. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:19-24 [Conf]
  8. Samy Meftali, Jean-Luc Dekeyser
    An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:55-58 [Conf]
  9. Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
    An MPSoC Performance Estimation Framework Using Transaction Level Modeling. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:525-533 [Conf]

  10. MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  11. Using an MDE Approach for Modeling of Interconnection Networks. [Citation Graph (, )][DBLP]


  12. Scalable Multistage Network for Multiprocessor System-on-Chip Design. [Citation Graph (, )][DBLP]


  13. SOAP Based Distributed Simulation Environment for SoC Design. [Citation Graph (, )][DBLP]


  14. Embed Scripting inside SystemC. [Citation Graph (, )][DBLP]


  15. An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). [Citation Graph (, )][DBLP]


  16. MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. [Citation Graph (, )][DBLP]


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