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Publications of Author

1. Chen-Yong Cher, Il Park, T. N. Vijaykumar
   Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. [Citation Graph (0, 0)][DBLP]
   ARCS, 2006, pp:232-251 [Conf]
   
2. Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykumar
   Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 2004, pp:199-210 [Conf]
   
3. Chen-Yong Cher, T. N. Vijaykumar
   Skipper: a microarchitecture for exploiting control-flow independence. [Citation Graph (0, 0)][DBLP]
   MICRO, 2001, pp:4-15 [Conf]
   
4. Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
   VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. [Citation Graph (0, 0)][DBLP]
   MICRO, 2003, pp:19-28 [Conf]
   
5. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
   An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:347-358 [Conf]
   
6. Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar
   Combined circuit and architectural level variable supply-voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:564-576 [Journal]
   
7. 
   Performance and power evaluation of an in-line accelerator. [Citation Graph (, )][DBLP]
   
   
8. 
   Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]
   
   
9. 
   Variation-aware thermal characterization and management of multi-core architectures. [Citation Graph (, )][DBLP]
   
   
10. 
    Software-Controlled Priority Characterization of POWER5 Processor. [Citation Graph (, )][DBLP]
    
    
11. 
    Thermal-aware task scheduling at the system software level. [Citation Graph (, )][DBLP]
    
    
12. 
    Cell GC: using the cell synergistic processor as a garbage collection coprocessor. [Citation Graph (, )][DBLP]