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Christopher Claus: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christopher Claus, Florian Helmut Müller, Walter Stechele
    Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:122-131 [Conf]
  2. Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
    Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:41-46 [Conf]
  3. Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele
    Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:498-503 [Conf]
  4. Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele
    A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  5. Christopher Claus, Walter Stechele, Andreas Herkersdorf
    Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:181-0 [Journal]

  6. Reconfigurable Processing Units vs. Reconfigurable Interconnects. [Citation Graph (, )][DBLP]


  7. Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. [Citation Graph (, )][DBLP]


  8. A comparison of embedded reconfigurable video-processing architectures. [Citation Graph (, )][DBLP]


  9. A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. [Citation Graph (, )][DBLP]


  10. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  11. Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. [Citation Graph (, )][DBLP]


  12. Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. [Citation Graph (, )][DBLP]


  13. Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. [Citation Graph (, )][DBLP]


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