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Walter Stechele :
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Christopher Claus , Florian Helmut Müller , Walter Stechele Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. [Citation Graph (0, 0)][DBLP ] ARCS Workshops, 2006, pp:122-131 [Conf ] Gabriel Lipsa , Andreas Herkersdorf , Wolfgang Rosenstiel , Oliver Bringmann , Walter Stechele Towards a Framework and a Design Methodology for Autonomous SoC. [Citation Graph (0, 0)][DBLP ] ARCS Workshops, 2005, pp:101-108 [Conf ] Walter Stechele , Stephan Herrmann , Andreas Herkersdorf Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing. [Citation Graph (0, 0)][DBLP ] ARCS Workshops, 2004, pp:225-234 [Conf ] Peter M. Kuhn , Andreas Weisgerber , Robert Poppenwimmer , Walter Stechele A flexible VLSI architecture for variable block size segment matching with luminance correction. [Citation Graph (0, 0)][DBLP ] ASAP, 1997, pp:479-488 [Conf ] Andreas Herkersdorf , Walter Stechele AutoVision: flexible processor architecture for video-assisted driving. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:556- [Conf ] Walter Stechele , L. Alvado Cárcel , Stephan Herrmann , J. Lidón Simón A Coprocessor for Accelerating Visual Information Processing. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:26-31 [Conf ] Paul Zuber , Armin Windschiegl , Raúl Medina Beltán de Otálora , Walter Stechele , Andreas Herkersdorf Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:986-987 [Conf ] Ulrich Niedermeier , Jörg Heuer , Anreas Hutter , Walter Stechele MPEG-7 Binary Format for XML Dat. [Citation Graph (0, 0)][DBLP ] DCC, 2002, pp:467- [Conf ] Paul Zuber , Florian Helmut Müller , Walter Stechele Optimization Potential of CMOS Power by Wire Spacing. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (1), 2005, pp:344-348 [Conf ] Andreas Bernauer , Oliver Bringmann , Wolfgang Rosenstiel , Abdelmajid Bouajila , Walter Stechele , Andreas Herkersdorf An Architecture for Runtime Evaluation of SoC Reliability. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (1), 2006, pp:177-0 [Conf ] Gabriel Lipsa , Andreas Herkersdorf , Wolfgang Rosenstiel , Oliver Bringmann , Walter Stechele Towards a Framework and a Design Methodology for Autonomic SoC. [Citation Graph (0, 0)][DBLP ] ICAC, 2005, pp:391-392 [Conf ] Michael Eiermann , Walter Stechele Novel modeling techniques for RTL power estimation. [Citation Graph (0, 0)][DBLP ] ISLPED, 2002, pp:323-328 [Conf ] Michael Hübner , Lars Braun , Jürgen Becker , Christopher Claus , Walter Stechele Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2007, pp:41-46 [Conf ] Torsten Mahnke , Walter Stechele , Wolfgang Hoeld Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. [Citation Graph (0, 0)][DBLP ] PATMOS, 2002, pp:146-155 [Conf ] Armin Windschiegl , Paul Zuber , Walter Stechele Exploiting Metal Layer Characteristics for Low-Power Routing. [Citation Graph (0, 0)][DBLP ] PATMOS, 2002, pp:55-64 [Conf ] Paul Zuber , Peter Gritzmann , Michael Ritter , Walter Stechele The Optimal Wire Order for Low Power CMOS. [Citation Graph (0, 0)][DBLP ] PATMOS, 2005, pp:674-683 [Conf ] Walter Stechele Performance Optimization of Color Segmentation Algorithms. [Citation Graph (0, 0)][DBLP ] SIP, 2003, pp:292-297 [Conf ] Christopher Claus , Johannes Zeppenfeld , Florian Helmut Müller , Walter Stechele Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:498-503 [Conf ] Christopher Claus , Florian Helmut Müller , Johannes Zeppenfeld , Walter Stechele A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-7 [Conf ] Abdelmajid Bouajila , Johannes Zeppenfeld , Walter Stechele , Andreas Herkersdorf , Andreas Bernauer , Oliver Bringmann , Wolfgang Rosenstiel Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP ] VLSI-SoC, 2006, pp:338-341 [Conf ] Walter Stechele , L. Alvado Cárcel , Stephan Herrmann , J. Lidón Simón A Coprocessor for Accelerating Visual Information Processing [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Christopher Claus , Walter Stechele , Andreas Herkersdorf Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). [Citation Graph (0, 0)][DBLP ] it - Information Technology, 2007, v:49, n:3, pp:181-0 [Journal ] Dynamically Reconfigurable Systems-on-Chip. [Citation Graph (, )][DBLP ] Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. [Citation Graph (, )][DBLP ] Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. [Citation Graph (, )][DBLP ] A rapid prototyping system for error-resilient multi-processor systems-on-chip. [Citation Graph (, )][DBLP ] A comparison of embedded reconfigurable video-processing architectures. [Citation Graph (, )][DBLP ] A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. [Citation Graph (, )][DBLP ] Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP ] Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. [Citation Graph (, )][DBLP ] Learning Classifier Tables for Autonomic Systems on Chip. [Citation Graph (, )][DBLP ] Workshop "Adaptive and Organic Systems". [Citation Graph (, )][DBLP ] Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. [Citation Graph (, )][DBLP ] Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. [Citation Graph (, )][DBLP ] Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. [Citation Graph (, )][DBLP ] Toward contextual forensic retrieval for visual surveillance: Challenges and an architectural approach. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.005secs