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Jürgen Becker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn
    Digital On-Demand Computing Organism for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:230-245 [Conf]
  2. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Universal Sequencer Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS, 1997, pp:143-152 [Conf]
  3. Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker
    Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:39-44 [Conf]
  4. Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu
    Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. [Citation Graph (0, 0)][DBLP]
    ARCS, 1999, pp:143-154 [Conf]
  5. Alexander Thomas, Jürgen Becker
    Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:165-174 [Conf]
  6. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
    A Synthesis System For Bus-Based Wavefront Array Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:274-283 [Conf]
  7. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Sequencer Hardware for Application Specific Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:392-401 [Conf]
  8. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
    A Parallelizing Compilation Method for the Map-oriented Machine. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:129-132 [Conf]
  9. Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
    Parallelization in Co-Compilation for Configurable Accelerators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:23-33 [Conf]
  10. Reiner W. Hartenstein, Jürgen Becker
    Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:141-146 [Conf]
  11. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
    Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:77-84 [Conf]
  12. Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
    HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:29-33 [Conf]
  13. Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten
    An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11120-11121 [Conf]
  14. Michael Ullmann, Wansheng Jin, Jürgen Becker
    Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:259-264 [Conf]
  15. Michael Ullmann, Wansheng Jin, Jürgen Becker
    Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:259-264 [Conf]
  16. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
    Two-Level Hardware/Software Partitioning Using CoDe-X. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:395-0 [Conf]
  17. Jürgen Becker, Martin Vorbach
    PACT XPP Architecture in Adaptive System-on-Chip Integration. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:21-30 [Conf]
  18. Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner
    Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:205-216 [Conf]
  19. Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:703-706 [Conf]
  20. Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
    Perspectives of Reconfigurable Computing in Research, Industry and Education. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:39-48 [Conf]
  21. Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
    Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:584-589 [Conf]
  22. Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
    Data-Procedural Languages for FPL-based Machines. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:183-195 [Conf]
  23. Jürgen Becker, Thilo Pionteck, Manfred Glesner
    DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:312-321 [Conf]
  24. Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker
    Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:507-513 [Conf]
  25. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    Data scheduling to increase performance of parallel accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:294-303 [Conf]
  26. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
    Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:65-76 [Conf]
  27. Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker
    Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1037-1041 [Conf]
  28. Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein
    FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:25-30 [Conf]
  29. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Field Programmable Communication Emulation and Optimization for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:58-67 [Conf]
  30. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:179-188 [Conf]
  31. Alexander Thomas, Jürgen Becker
    Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:115-124 [Conf]
  32. Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
    On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:454-463 [Conf]
  33. Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer
    CARUSO - Project Goals and Principal Approach. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2004, pp:616-620 [Conf]
  34. Reiner W. Hartenstein, Jürgen Becker
    A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1997, pp:125-134 [Conf]
  35. Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis
    Distributed Collaborative Design over Cave2 Framework. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:97-108 [Conf]
  36. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:659-670 [Conf]
  37. Uwe Brinkschulte, Jürgen Becker, Theo Ungerer
    CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  38. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
    A Partitioning Programming Environment for a Novel Parallel Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:544-548 [Conf]
  39. Michael Hübner, Katarina Paulsson, Jürgen Becker
    Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  40. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:61-66 [Conf]
  41. Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
    An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  42. Michael Ullmann, Wansheng Jin, Jürgen Becker
    Hardware Enhanced Function Allocation Management in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  43. Martin Vorbach, Jürgen Becker
    Reconfigurable Processor Architectures for Mobile Phones. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:181- [Conf]
  44. M. Hübner, C. Schuck, J. Becker
    Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  45. Maik Boden, Steffen Rülke, Jürgen Becker
    A high-level target-precise model for designing reconfigurable HW tasks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  46. Jürgen Becker, Martin Vorbach
    Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:107-112 [Conf]
  47. Alexander Thomas, Jürgen Becker
    Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:118-123 [Conf]
  48. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A Two-Level Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:109-116 [Conf]
  49. Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker
    Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:159-166 [Conf]
  50. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker
    Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:251-256 [Conf]
  51. Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker
    New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:97-102 [Conf]
  52. Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
    Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:41-46 [Conf]
  53. Alisson V. De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher
    Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:35-40 [Conf]
  54. Jens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker
    Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:134-135 [Conf]
  55. Carsten Bieser, Klaus D. Müller-Glaser, Jürgen Becker
    Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:51-52 [Conf]
  56. Jochen Mades, T. Schneider, A. Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner
    Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:2-3 [Conf]
  57. Jürgen Becker, Manfred Glesner
    IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  58. Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk
    Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  59. Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas
    Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:35-42 [Conf]
  60. Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein
    Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:46-51 [Conf]
  61. Chun Hok Ho, M. P. Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner
    Rapid Prototyping of FPGA Based Floating Point DSP Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:19-24 [Conf]
  62. Jürgen Becker, Reiner W. Hartenstein
    Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:32-38 [Conf]
  63. Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner
    Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:160-0 [Conf]
  64. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:52-57 [Conf]
  65. Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner
    Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:58-63 [Conf]
  66. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:154-159 [Conf]
  67. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:108-113 [Conf]
  68. J. Becker, M. Hübner
    Run-time reconfigurabilility and other future trends. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:9-11 [Conf]
  69. Alexander Thomas, Thomas Zander, Jürgen Becker
    Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:141-146 [Conf]
  70. M. Hübner, J. Becker
    Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:1-4 [Conf]
  71. Katarina Paulsson, Michael Hübner, Jürgen Becker
    On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:173-178 [Conf]
  72. Michael Hübner, Tobias Becker, Jürgen Becker
    Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:28-32 [Conf]
  73. Jürgen Becker, Michael Hübner, Michael Ullmann
    Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:283-288 [Conf]
  74. Jürgen Becker, Alexander Thomas, Maik Scheer
    Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:237-242 [Conf]
  75. Jürgen Becker, Michael Hübner, Michael Ullmann
    Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:129-0 [Conf]
  76. Jürgen Becker, Alexander Thomas, Maik Scheer
    Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:288-0 [Conf]
  77. Reiner W. Hartenstein, Jürgen Becker
    Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:146-150 [Conf]
  78. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
    CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:81-84 [Conf]
  79. Katarina Paulsson, Michael Hübner, Jürgen Becker
    Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:288-291 [Conf]
  80. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
    High-performance computing using a reconfigurable accelerator. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1996, v:8, n:6, pp:429-443 [Journal]
  81. Jürgen Becker, Alexander Thomas
    Scalable Processor Instruction Set Extension. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:2, pp:136-148 [Journal]
  82. Jürgen Becker
    Dagstuhl-Seminar "Dynamically and Partially Reconfigurable Architectures". [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2004, v:46, n:4, pp:218-225 [Journal]
  83. Jürgen Becker, Kurt Brändle, Michael Ullmann
    Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2005, v:47, n:4, pp:201-206 [Journal]
  84. Jürgen Becker, Reiner W. Hartenstein
    Configware and morphware going mainstream. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:4-6, pp:127-142 [Journal]
  85. Jürgen Becker, Manfred Glesner
    A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2001, v:19, n:1, pp:105-127 [Journal]
  86. Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
    From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  87. Alisson V. De Brito, Matthias Kühnle, Elmar U. K. Melcher, Jürgen Becker
    A General Purpose Partially Reconfigurable Processor Simulator (PReProS). [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  88. Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker
    High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  89. Carlos Morra, João M. P. Cardoso, Jürgen Becker
    Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  90. Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker
    Communication Architectures for Dynamically Reconfigurable FPGA Designs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  91. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  92. Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker
    Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:1-6 [Conf]
  93. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:93-98 [Conf]
  94. Michael Ullmann, Wansheng Jin, Jürgen Becker
    Hardware Support for QoS-based Function Allocation in Reconfigurable Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  95. Alexander Thomas, Jürgen Becker
    New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:165-0 [Journal]

  96. A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA. [Citation Graph (, )][DBLP]


  97. QUKU: A Coarse Grained Paradigm for FPGAs. [Citation Graph (, )][DBLP]


  98. 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  99. 06141 Executive Summary -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  100. Physical 2D Morphware and Power Reduction Methods for Everyone. [Citation Graph (, )][DBLP]


  101. Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. [Citation Graph (, )][DBLP]


  102. Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. [Citation Graph (, )][DBLP]


  103. A System Architecture for Reconfigurable Trusted Platforms. [Citation Graph (, )][DBLP]


  104. Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. [Citation Graph (, )][DBLP]


  105. A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. [Citation Graph (, )][DBLP]


  106. Priority-based packet communication on a bus-shaped structure for FPGA-systems. [Citation Graph (, )][DBLP]


  107. Scenario extraction for a refined timing-analysis of automotive network topologies. [Citation Graph (, )][DBLP]


  108. KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. [Citation Graph (, )][DBLP]


  109. Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era. [Citation Graph (, )][DBLP]


  110. Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  111. A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  112. artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. [Citation Graph (, )][DBLP]


  113. Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. [Citation Graph (, )][DBLP]


  114. On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. [Citation Graph (, )][DBLP]


  115. MORPHEUS: Heterogeneous Reconfigurable Computing. [Citation Graph (, )][DBLP]


  116. Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. [Citation Graph (, )][DBLP]


  117. H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  118. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]


  119. Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. [Citation Graph (, )][DBLP]


  120. New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. [Citation Graph (, )][DBLP]


  121. A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. [Citation Graph (, )][DBLP]


  122. Data path driven waveform-like reconfiguration. [Citation Graph (, )][DBLP]


  123. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  124. Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. [Citation Graph (, )][DBLP]


  125. Dynamic reconfigurable mixed-signal architecture for safety critical applications. [Citation Graph (, )][DBLP]


  126. Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. [Citation Graph (, )][DBLP]


  127. Runtime adaptive multi-processor system-on-chip: RAMPSoC. [Citation Graph (, )][DBLP]


  128. A framework for dynamic 2D placement on FPGAs. [Citation Graph (, )][DBLP]


  129. An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. [Citation Graph (, )][DBLP]


  130. A self adaptive interfacing concept for consumer device integration into automotive entities. [Citation Graph (, )][DBLP]


  131. A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. [Citation Graph (, )][DBLP]


  132. Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. [Citation Graph (, )][DBLP]


  133. Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. [Citation Graph (, )][DBLP]


  134. A Web Server Based Edge Detector Implementation in FPGA. [Citation Graph (, )][DBLP]


  135. Towards Novel Approaches in Design Automation for FPGA Power Optimization. [Citation Graph (, )][DBLP]


  136. Configuration Measurement for FPGA-based Trusted Platforms. [Citation Graph (, )][DBLP]


  137. A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates. [Citation Graph (, )][DBLP]


  138. Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation. [Citation Graph (, )][DBLP]


  139. System concept for an FPGA based real-time capable automotive ECU simulation system. [Citation Graph (, )][DBLP]


  140. New tool support and architectures in adaptive reconfigurable computing. [Citation Graph (, )][DBLP]


  141. Car-to-Car Communication Security on Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  142. FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. [Citation Graph (, )][DBLP]


  143. Data reallocation by exploiting FPGA configuration mechanisms. [Citation Graph (, )][DBLP]


  144. Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. [Citation Graph (, )][DBLP]


  145. An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. [Citation Graph (, )][DBLP]


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