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Publications of Author

1. Klaus Danne
   Operating Systems for FPGA Based Computers and Their Memory. [Citation Graph (0, 0)][DBLP]
   ARCS Workshops, 2004, pp:195-204 [Conf]
   
2. Klaus Danne, Christophe Bobda, Heiko Kalte
   Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System. [Citation Graph (0, 0)][DBLP]
   Engineering of Reconfigurable Systems and Algorithms, 2003, pp:147-153 [Conf]
   
3. Christophe Bobda, Klaus Danne, André Linarth
   Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:1123-1126 [Conf]
   
4. Klaus Danne, Christophe Bobda, Heiko Kalte
   Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:272-281 [Conf]
   
5. Klaus Danne, Marco Platzner
   A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:568-573 [Conf]
   
6. Tales Heimfarth, Klaus Danne, Franz J. Rammig
   An OS for Mobile Ad hoc Networks Using Ant Based Hueristic to Distribute Mobile Services. [Citation Graph (0, 0)][DBLP]
   ICAS/ICNS, 2005, pp:77- [Conf]
   
7. Klaus Danne, Christophe Bobda
   Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-Off Analysis. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2004, pp:- [Conf]
   
8. Klaus Danne, Marco Platzner
   Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
9. Klaus Danne, Marco Platzner
   An EDF schedulability test for periodic tasks on reconfigurable hardware devices. [Citation Graph (0, 0)][DBLP]
   LCTES, 2006, pp:93-102 [Conf]
   
10. Klaus Danne
    Distributed arithmetic FPGA design with online scalable size and performance. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:135-140 [Conf]
    
11. Klaus Danne, Marco Platzner
    Periodic Real-Time Scheduling for FPGA Computers. [Citation Graph (0, 0)][DBLP]
    WISES, 2005, pp:117-127 [Conf]
    
12. Klaus Danne, Roland Muhlenbernd, Marco Platzner
    Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
    
13. 
    Architecting a chunk-based memory race recorder in modern CMPs. [Citation Graph (, )][DBLP]