The SCEAS System
Navigation Menu

Search the dblp DataBase


Masayasu Suzuki: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano
    Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:12-18 [Conf]
  2. Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki
    Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:315-316 [Conf]
  3. Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
    Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:328-329 [Conf]
  4. Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano
    Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:265- [Conf]
  5. Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki
    Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:464-473 [Conf]
  6. Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano
    RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:129-136 [Conf]
  7. Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano
    A cost-effective context memory structure for dynamically reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]

  8. Controlling ideal turbulence in time-delayed chua's circuits and an application to communications. [Citation Graph (, )][DBLP]

Search in 0.041secs, Finished in 0.041secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002