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Kenichiro Anjo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano
    Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:12-18 [Conf]
  2. Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura
    Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. [Citation Graph (0, 0)][DBLP]
    EUC, 2004, pp:301-311 [Conf]
  3. Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
    Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:328-329 [Conf]
  4. Hideharu Amano, Akiya Jouraku, Kenichiro Anjo
    A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:161-170 [Conf]
  5. Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo
    Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:171-180 [Conf]
  6. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
    An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:163-170 [Conf]
  7. Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  8. Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
    A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:12, pp:1425-1437 [Journal]

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