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Jörg Keller: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fernando de Ferreira Rezende, Georgiane de Sá Oliveira, Renata Costa Guedes Pereira, Ulrich Hermsen, Jörg Keller
    A Unified Database Interface for Multiple Heterogeneous Databases. [Citation Graph (1, 0)][DBLP]
    EFIS, 1999, pp:61-78 [Conf]
  2. Ingrid Biehl, Jörg Keller
    Effizienzverbesserungen durch schlüssel-optimierte Ver- und Entschlüsselung in Workstations. [Citation Graph (0, 0)][DBLP]
    ARCS, 1999, pp:279-283 [Conf]
  3. Latifa Boursas, Jörg Keller
    Implementation and Evaluation of a Parallel-External Algorithm for Cycle Structure Computation on a PC-Cluster. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:348-357 [Conf]
  4. Andreas Grävinghoff, Jörg Keller
    Virtual Duplex Systems in Embedded Environments. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 1999, pp:69-77 [Conf]
  5. Jörg Keller, Johannes Magauer
    Error-Correcting Codes in Steganography. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:52-55 [Conf]
  6. Jörg Keller, Milan Manasijevic
    A New Data Structure for Shannon Decomposition. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 1999, pp:109-116 [Conf]
  7. Christof Meigen, Jörg Keller
    A simple parallel algorithm for the stepwise approximate computation of Voronoi diagrams of line segments. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:305-312 [Conf]
  8. Jörg Keller, Tobias Eggendorfer
    Combining SMTP and HTTP tar Pits to Proactively Reduce Spam. [Citation Graph (0, 0)][DBLP]
    Security and Management, 2006, pp:300-306 [Conf]
  9. Norbert Lehmann, Reinhard Schwarz, Jörg Keller
    FireCrocodile: A Checker for Static Firewall Configurations. [Citation Graph (0, 0)][DBLP]
    Security and Management, 2006, pp:193-199 [Conf]
  10. Ferri Abolhassan, Jörg Keller, Wolfgang J. Paul
    Überblick über PRAM-Simulationen und ihre Realisierbarkeit. [Citation Graph (0, 0)][DBLP]
    Entwurf und Betrieb verteilter Systeme, 1990, pp:15-39 [Conf]
  11. Arno Formella, Jörg Keller, Thomas Walle
    HPP: A High Performance PRAM. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:425-434 [Conf]
  12. Jörg Keller, Jop F. Sibeyn
    Beyond External Computing: Analysis of the Cycle Structure of Permutations. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:333-342 [Conf]
  13. Arno Formella, Jörg Keller
    Generalized Fisheye Views of Graphs. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 1995, pp:242-253 [Conf]
  14. Jörg Keller, Andreas Grävinghoff
    Evaluation of Thread-Based Virtual Duplex Systems in Embedded Environments. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (Schwerpunkt "Sicherheit - Schutz und Zuverlässigkeit"), 2003, pp:151-162 [Conf]
  15. Reinhard Drefenstedt, Jörg Keller, Wolfgang J. Paul
    Applications of PRAMs in Telecommunications. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1994, pp:203-210 [Conf]
  16. P. Bergmann, Jörg Keller, T. Malter, Silvia M. Müller, Wolfgang J. Paul, Thorsten Pöschel, O. Schlüter, L. Thiele
    Implementierung eines informationstheoretischen Ansatzes zur Bilderkennung. [Citation Graph (0, 0)][DBLP]
    Innovative Informations-Infrastrukturen, 1988, pp:187-197 [Conf]
  17. Bernhard Fechner, Jörg Keller, Peter Sobe
    Performance Estimation of Virtual Duplex Systems on Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  18. Bernhard Fechner, Jörg Keller, Andreas Wohlfeld
    Web server protection by customized instruction set encoding. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  19. Arno Formella, Jörg Keller
    Parallel Software Caches. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1997, pp:219-232 [Conf]
  20. Jörg Keller, Thomas Rauber, Bernd Rederlechner
    Conservative Circuit Simulation on Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Simulation, 1996, pp:126-134 [Conf]
  21. Bernhard Fechner, Jörg Keller
    A Fault-Tolerant Voting Scheme for Multithreaded Environments. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:237-239 [Conf]
  22. Curd Engelmann, Jörg Keller
    Simulation-based Comparison of Hash Functions for Emulated Shared Memory. [Citation Graph (0, 0)][DBLP]
    PARLE, 1993, pp:1-11 [Conf]
  23. Jörg Keller, Olaf Monien
    Improving http-server performance by adapted multithreading. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2004, pp:631-636 [Conf]
  24. Jörg Keller, Valerij Bauer, Wojciech Kwedlo
    Application of Data-Mining and Knowledge Discovery in Automotive Data Engineering. [Citation Graph (0, 0)][DBLP]
    PKDD, 2000, pp:464-469 [Conf]
  25. Stephan Diehl, Jörg Keller
    VRML with constraints. [Citation Graph (0, 0)][DBLP]
    Web3D, 2000, pp:81-86 [Conf]
  26. Jörg Keller, Wolfgang J. Paul, Dieter Scheerer
    Realization of PRAMs: Processor Design. [Citation Graph (0, 0)][DBLP]
    WDAG, 1994, pp:17-27 [Conf]
  27. Tobias Eggendorfer, Jörg Keller
    Dynamically blocking access to web pages for spammers' harvesters. [Citation Graph (0, 0)][DBLP]
    Communication, Network, and Information Security, 2006, pp:205-210 [Conf]
  28. Jörg Keller, Ralf Naues
    Design of a virtual computer security lab. [Citation Graph (0, 0)][DBLP]
    Communication, Network, and Information Security, 2006, pp:211-215 [Conf]
  29. Ferri Abolhassan, Jörg Keller, Wolfgang J. Paul
    On the Cost-Effectiveness of PRAMs. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1999, v:36, n:6, pp:463-487 [Journal]
  30. Ferri Abolhassan, Reinhard Drefenstedt, Jörg Keller, Wolfgang J. Paul, Dieter Scheerer
    On the Physical Design of PRAMs. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1993, v:36, n:8, pp:756-762 [Journal]
  31. David Cross, Reinhard Drefenstedt, Jörg Keller
    Reduction of Network Cost and Wiring in Ranade's Butterfly Routing. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1993, v:45, n:2, pp:63-67 [Journal]
  32. Jörg Keller
    A heuristic to accelerate in-situ permutation algorithms. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:81, n:3, pp:119-125 [Journal]
  33. Jörg Keller, Thomas Walle
    A Note on Implementing Combining Networks. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1995, v:55, n:4, pp:195-200 [Journal]
  34. Udo Hönig, Jörg Keller, Wolfram Schiffmann
    Internet-basierter Übungsbetrieb in Technischer Informatik (Web-Based Exercises in Computer Engineering). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2004, v:46, n:5, pp:255-264 [Journal]
  35. Klaus Echtle, Jörg Keller
    J.UCS Special Issue on Dependability Evaluation and Validation. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1999, v:5, n:10, pp:632- [Journal]
  36. Jörg Keller, Theo Ungerer
    J.UCS Special Issue on Multithreaded Processors and Chip-Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2000, v:6, n:10, pp:906-907 [Journal]
  37. Bernd Rederlechner, Jörg Keller
    A Note on Correctness Proofs for Overflow Detection Logic in Adders for d-th Complement Numbers. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1997, v:3, n:10, pp:1121-1125 [Journal]
  38. Torben Hagerup, Jörg Keller
    Fast Parallel Permutation Algorithms. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1995, v:5, n:, pp:139-148 [Journal]
  39. Jörg Keller
    Fast Rehashing in PRAM Emulations. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1996, v:155, n:2, pp:349-363 [Journal]
  40. Jörg Keller, Ralf Naues
    A Collaborative Virtual Computer Security Lab. [Citation Graph (0, 0)][DBLP]
    e-Science, 2006, pp:126- [Conf]
  41. Johannes Jendrsczok, Rolf Hoffmann, Jörg Keller
    Hirschberg's Algorithm on a GCA and Its Parallel Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2007, pp:815-824 [Conf]
  42. Johannes Jendrsczok, Rolf Hoffmann, Jörg Keller
    Implementing Hirschberg's PRAM-Algorithm for Connected Components on a Global Cellular Automaton. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]

  43. Hybrid Parallel Sort on the Cell Processor. [Citation Graph (, )][DBLP]


  44. Optimized Pipelined Parallel Merge Sort on the Cell BE. [Citation Graph (, )][DBLP]


  45. Optimized On-Chip-Pipelined Mergesort on the Cell/B.E. [Citation Graph (, )][DBLP]


  46. Fault-tolerant static scheduling for grids. [Citation Graph (, )][DBLP]


  47. Guiding performance tuning for grid schedules. [Citation Graph (, )][DBLP]


  48. Storage architecture with integrity, redundancy and encryption. [Citation Graph (, )][DBLP]


  49. On the cost-effectiveness of PRAMs. [Citation Graph (, )][DBLP]


  50. Remote operation and control of computer engineering laboratory experiments. [Citation Graph (, )][DBLP]


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