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Publications of Author

1. Florian Dittmann, Tales Heimfarth
   Clock Frequency Variation of Partially Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
   ARCS Workshops, 2006, pp:195-204 [Conf]
   
2. Florian Dittmann, Achim Rettberg, Fabian Schulte
   A Y-Chart Based Tool for Reconfigurable System Design. [Citation Graph (0, 0)][DBLP]
   ARCS Workshops, 2005, pp:67-73 [Conf]
   
3. Florian Dittmann, Achim Rettberg, Thomas Lehmann, Mauro Cesar Zanella
   Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture. [Citation Graph (0, 0)][DBLP]
   DELTA, 2004, pp:245-250 [Conf]
   
4. Stefan Ihmor, Florian Dittmann
   Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
   ERSA, 2005, pp:85-91 [Conf]
   
5. Florian Dittmann, Achim Rettberg, Raphael Weber
   Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. [Citation Graph (0, 0)][DBLP]
   EUC, 2005, pp:448-457 [Conf]
   
6. Florian Dittmann
   Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:717-718 [Conf]
   
7. Florian Dittmann, Achim Rettberg
   A Self-Controlled and Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   DIPES, 2004, pp:207-216 [Conf]
   
8. Florian Dittmann, Marcelo Götz
   Applying single processor algorithms to schedule tasks on reconfigurable devices respecting reconfiguration times. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
9. Alexander Warkentin, Florian Dittmann
   Data Transfer Protocols for a Two Slot Based Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:8-15 [Conf]
   
10. Florian Dittmann, Markus Heberling
    Placement of intermodule connections on partially reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:236-241 [Conf]
    
11. Achim Rettberg, Florian Dittmann, Mauro Cesar Zanella, Thomas Lehmann
    Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:79-84 [Conf]
    
12. Florian Dittmann, Stefan Frank
    Hard real-time reconfiguration port scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:123-128 [Conf]
    
13. Florian Dittmann, Marcelo Götz, Achim Rettberg
    Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
    
14. Marcelo Götz, Tao Xie, Florian Dittmann
    Dynamic Relocation of Hybrid Tasks: A Complete Design Flow. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:31-38 [Conf]
    
15. Florian Dittmann
    Algorithmic Skeletons for the Programming of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    SEUS, 2007, pp:358-367 [Conf]
    
16. Marcelo Götz, Florian Dittmann
    Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:255-261 [Conf]
    
17. Florian Dittmann, Franz-Josef Rammig, M. Streubühr, Christian Haubelt, Andreas Schallenberg, Wolfgang Nebel
    Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:149-0 [Journal]
    
18. 
    Reconfiguration Time Aware Processing on FPGAs. [Citation Graph (, )][DBLP]
    
    
19. 
    Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs. [Citation Graph (, )][DBLP]
    
    
20. 
    Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture. [Citation Graph (, )][DBLP]
    
    
21. 
    Implementation of the reconfiguration port scheduling on the erlangen slot machine. [Citation Graph (, )][DBLP]
    
    
22. 
    Caching in Real-time Reconfiguration Port Scheduling. [Citation Graph (, )][DBLP]
    
    
23. 
    Algorithmic skeletons for the design of partially reconfigurable systems. [Citation Graph (, )][DBLP]
    
    
24. 
    Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. [Citation Graph (, )][DBLP]
    
    
25. 
    Towards Advanced Information Fusion for Driver Assistant Systems of Modern Vehicles. [Citation Graph (, )][DBLP]
    
    
26. 
    State Machine Based Method for Consolidating Vehicle Data. [Citation Graph (, )][DBLP]
    
    
27. 
    Part-E - A Tool for Reconfigurable System Design. [Citation Graph (, )][DBLP]