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Achim Rettberg: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Florian Dittmann, Achim Rettberg, Fabian Schulte
    A Y-Chart Based Tool for Reconfigurable System Design. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:67-73 [Conf]
  2. Achim Rettberg, Wolfgang Thronicke
    Embedded System Design Based On Webservices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:232-237 [Conf]
  3. Achim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann
    A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11130-11131 [Conf]
  4. Tim Schattkowsky, Wolfgang Müller 0003, Achim Rettberg
    A Model-Based Approach for Executable Specifications on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:692-697 [Conf]
  5. Florian Dittmann, Achim Rettberg, Thomas Lehmann, Mauro Cesar Zanella
    Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:245-250 [Conf]
  6. Natascha Petry Ligocki, Achim Rettberg, Mauro Cesar Zanella, Andreas Hennig, André Luiz de Freitas Francisco
    Towards a Modular Communication System for FPGAs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:71-76 [Conf]
  7. Achim Rettberg, Franz J. Rammig
    A new Design Partitioning Approach for Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:143-148 [Conf]
  8. Marcelo Götz, Achim Rettberg, Carlos Eduardo Pereira
    A Run-Time Partitioning Algorithm for RTOS on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:469-478 [Conf]
  9. Florian Dittmann, Achim Rettberg, Raphael Weber
    Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:448-457 [Conf]
  10. Achim Rettberg, Bernd Kleinjohann, Franz J. Rammig
    Spezielle Aspekte der Verlustleistungsgetriebenen High-Level Synthese. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:455- [Conf]
  11. Florian Dittmann, Achim Rettberg
    A Self-Controlled and Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:207-216 [Conf]
  12. André Luiz de Freitas Francisco, Achim Rettberg, Andreas Hennig
    Hardware Design and Protocol Specification for the Control and Communication within a Mechatronic System. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:113-122 [Conf]
  13. Achim Rettberg, Bernd Kleinjohann, Franz J. Rammig
    Integration of Low Power Analysis into High-Level Scheduling in Distributed Real-Time Computing Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2002, pp:205-215 [Conf]
  14. Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann
    The Specification Language SpecC within the PARADISE Design Environment. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:111-120 [Conf]
  15. Achim Rettberg, Wolfgang Thronicke
    How to integrate Webservices in Embedded System Design?. [Citation Graph (0, 0)][DBLP]
    DIPES, 2002, pp:267-276 [Conf]
  16. Carsten Rust, Achim Rettberg
    Automatic Synthesis of SystemC-Code from Formal Specifications. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:187-196 [Conf]
  17. Wolfram Hardt, Achim Rettberg, Bernd Kleinjohann
    The Re-Configurable Delay-Intensitive FLYSIG Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:703-705 [Conf]
  18. Wolfram Hardt, Bernd Kleinjohann, Achim Rettberg
    The FLYSIG Prototyping Approach. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:115-0 [Conf]
  19. Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Christophe Bobda
    A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:71-77 [Conf]
  20. Heiner Giefers, Achim Rettberg
    Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:113-118 [Conf]
  21. Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Ulrich Dierkes, Carsten Rustemeier
    Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:231-236 [Conf]
  22. Achim Rettberg, Florian Dittmann, Mauro Cesar Zanella, Thomas Lehmann
    Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:79-84 [Conf]
  23. Marcelo Götz, Achim Rettberg, Carlos Eduardo Pereira
    Communication-Aware Component Allocation Algorithm for a Hybrid Architecture. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:175-184 [Conf]
  24. Achim Rettberg, Franz-Josef Rammig
    Integration of Energy Reduction into High-Level Synthesis by Partitioning. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:225-234 [Conf]
  25. Henning Zabel, Achim Rettberg
    Prototyping an Ambient Light System - A Case Study. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:55-64 [Conf]
  26. Florian Dittmann, Marcelo Götz, Achim Rettberg
    Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  27. Richard Anthony, Achim Rettberg, De-Jiu Chen, Isabell Jahnich, Gerrit de Boer, Cecilia Ekelin
    Towards a Dynamically Reconfigurable Automotive Control System Architecture. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:71-84 [Conf]
  28. Isabell Jahnich, Achim Rettberg
    Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:97-106 [Conf]
  29. Henning Zabel, Achim Rettberg, Alexander Krupp
    Approach for a Formal Verification of a Bit-serial Pipelined Architecture. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:47-56 [Conf]

  30. Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs. [Citation Graph (, )][DBLP]

  31. Integrating Dynamic Load Balancing Strategies into the Car-Network. [Citation Graph (, )][DBLP]

  32. Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture. [Citation Graph (, )][DBLP]

  33. Seamless design flow for reconfigurable systems. [Citation Graph (, )][DBLP]

  34. Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. [Citation Graph (, )][DBLP]

  35. Overview of Multicore Requirements towards Real-Time Communication. [Citation Graph (, )][DBLP]

  36. Towards a Middleware Approach for a Self-configurable Automotive Embedded System. [Citation Graph (, )][DBLP]

  37. Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. [Citation Graph (, )][DBLP]

  38. Towards a Load Balancing Middleware for Automotive Infotainment Systems. [Citation Graph (, )][DBLP]

  39. Towards an Irritable Bowel Syndrome Control System Based on Artificial Neural Networks. [Citation Graph (, )][DBLP]

  40. Low-Level Space Optimization of an AES Implementation for a Bit-Serial Fully Pipelined Architecture. [Citation Graph (, )][DBLP]

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