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Reiner W. Hartenstein: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Reiner W. Hartenstein
    Konzepte der Mikroprogrammierung. [Citation Graph (0, 0)][DBLP]
    ARCS, 1974, pp:22-42 [Conf]
  2. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Universal Sequencer Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS, 1997, pp:143-152 [Conf]
  3. Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
    Xputers: An Open Family of Non-Von Neumann Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 1990, pp:45-58 [Conf]
  4. Reiner W. Hartenstein
    From Organic Computing to Reconfigurable Supercomputing. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:229-0 [Conf]
  5. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
    A Synthesis System For Bus-Based Wavefront Array Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:274-283 [Conf]
  6. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Sequencer Hardware for Application Specific Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:392-401 [Conf]
  7. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
    A Parallelizing Compilation Method for the Map-oriented Machine. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:129-132 [Conf]
  8. Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
    Parallelization in Co-Compilation for Configurable Accelerators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:23-33 [Conf]
  9. Reiner W. Hartenstein
    Coarse grain reconfigurable architecture (embedded tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:564-570 [Conf]
  10. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:163-168 [Conf]
  11. Reiner W. Hartenstein, Rainer Kress
    A datapath synthesis system for the reconfigurable datapath architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  12. Reiner W. Hartenstein
    The digital divide of computing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:357-362 [Conf]
  13. Reiner W. Hartenstein, Jürgen Becker
    Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:141-146 [Conf]
  14. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
    Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:77-84 [Conf]
  15. Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
    A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1990, pp:51-62 [Conf]
  16. Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Riedmüller, Karin Schmidt, M. Weber
    Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing. [Citation Graph (0, 0)][DBLP]
    DAGM-Symposium, 1990, pp:404-417 [Conf]
  17. Reiner W. Hartenstein
    A decade of reconfigurable computing: a visionary retrospective. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:642-649 [Conf]
  18. Reiner W. Hartenstein
    Reconfigurable Computing: A New Business Model and its Impact on SoC Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:103-111 [Conf]
  19. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
    Two-Level Hardware/Software Partitioning Using CoDe-X. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:395-0 [Conf]
  20. Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
    Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:211-217 [Conf]
  21. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:222- [Conf]
  22. Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
    Data-Procedural Languages for FPL-based Machines. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:183-195 [Conf]
  23. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    Data scheduling to increase performance of parallel accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:294-303 [Conf]
  24. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
    Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:65-76 [Conf]
  25. Reiner W. Hartenstein, Michael Herz, Frank Gilbert
    Designing for Xilinx XC6200 FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:29-38 [Conf]
  26. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:389-399 [Conf]
  27. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:189-198 [Conf]
  28. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Mapping Applications onto Reconfigurable Kress Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:385-390 [Conf]
  29. Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann
    An Internet Based Development Framework for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:155-164 [Conf]
  30. Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
    A New FPGA Architecture for Word-Oriented Datapaths. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:144-155 [Conf]
  31. Reiner W. Hartenstein
    Disruptive Trends by Data-Stream-Based Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:4- [Conf]
  32. Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
    An operating system for custom computing machines based on the Xputer paradigm. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:304-313 [Conf]
  33. Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein
    FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:25-30 [Conf]
  34. J. Dieckmann, Reiner W. Hartenstein, Werner Konrad
    Software-Zuverlässigkeit mit Rechnernetz-Baukästen verteilter Programmierung. [Citation Graph (0, 0)][DBLP]
    Hardware für Software, 1980, pp:188-197 [Conf]
  35. Reiner W. Hartenstein
    Hierarchy of Interpreters for Modelling Complex Digital Systems. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1973, pp:261-269 [Conf]
  36. Reiner W. Hartenstein
    Die "Neue Mikroelektronik" in der Informatik: Voraussetzungen und Auswirkungen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1982, pp:30-44 [Conf]
  37. Reiner W. Hartenstein, K. W. Jörg, U. Welters
    MLED - Ein Mehrebenen Graphik Editor für den VLSI-Entwurf. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:281-288 [Conf]
  38. Reiner W. Hartenstein, Peter Liell
    Ein Compiler für die Register Transfer-Sprache KARL-2. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1980, pp:559- [Conf]
  39. Reiner W. Hartenstein, Michael Ryba
    Partitionierungsschemata für Rechnerstrukturen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:246-262 [Conf]
  40. Reiner W. Hartenstein, Jürgen Becker
    A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1997, pp:125-134 [Conf]
  41. Reiner W. Hartenstein, Veljko M. Milutinovic
    Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  42. Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
    The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:609-610 [Conf]
  43. J. Bloedel, M. Brandstetter, Peter Conradi, W. Drangmeister, Reiner W. Hartenstein, D. Schroeder
    An Information Model Describing the Exchange of IC Technology Data. [Citation Graph (0, 0)][DBLP]
    Electronic Design Automation Frameworks, 1992, pp:9-19 [Conf]
  44. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
    A Partitioning Programming Environment for a Novel Parallel Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:544-548 [Conf]
  45. Reiner W. Hartenstein
    Are We Really Ready for the Breakthrough? [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:170- [Conf]
  46. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    On Reconfigurable Co-processing Units. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:67-72 [Conf]
  47. Reiner W. Hartenstein
    RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  48. Reiner W. Hartenstein
    Increasing Hardware Complexity - A Challenge to Computer Architecture Education. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:201-206 [Conf]
  49. Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson
    Flexibility and low power: a contradiction in terms? [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:375- [Conf]
  50. Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko
    The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:230-235 [Conf]
  51. Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger
    Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:118-128 [Conf]
  52. Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein
    Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:46-51 [Conf]
  53. Jürgen Becker, Reiner W. Hartenstein
    Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:32-38 [Conf]
  54. Reiner W. Hartenstein, Karin Schmidt
    Combining structural and procedural programming by parallelizing compilation. [Citation Graph (0, 0)][DBLP]
    SAC, 1995, pp:130-134 [Conf]
  55. Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
    Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:248-253 [Conf]
  56. Reiner W. Hartenstein
    The re-definition of low power design for HPC: a paradigm shift. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:7- [Conf]
  57. Mauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
    Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:205-210 [Conf]
  58. Mauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
    Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. [Citation Graph (0, 0)][DBLP]
    SCCC, 2003, pp:60-0 [Conf]
  59. Reiner W. Hartenstein, U. Welters
    Mehrebenenen-Graphik-Editor MLED als DBMS für VLSI-Simulation. [Citation Graph (0, 0)][DBLP]
    Simulationstechnik, 1987, pp:250-257 [Conf]
  60. Reiner W. Hartenstein, Jürgen Becker
    Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:146-150 [Conf]
  61. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
    CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:81-84 [Conf]
  62. Ricardo P. Jacobi, Mauricio Ayala-Rincón, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
    Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    WOB, 2004, pp:25-32 [Conf]
  63. William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
    Seeking Solutions in Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:38-43 [Journal]
  64. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
    High-performance computing using a reconfigurable accelerator. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1996, v:8, n:6, pp:429-443 [Journal]
  65. Reiner W. Hartenstein
    Synthese endlicher Automaten bei Problemen der Erkennung, Klassifikation und Informationsreduktion. [Citation Graph (0, 0)][DBLP]
    Elektronische Informationsverarbeitung und Kybernetik, 1971, v:7, n:5/6, pp:331-353 [Journal]
  66. Mauricio Ayala-Rincón, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein
    Applying ELAN Strategies in Simulating Processors over Simple Architectures. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2002, v:70, n:6, pp:- [Journal]
  67. Franz-Josef Brandenburg, Werner Freise, Winfried Görke, Reiner W. Hartenstein, P. Kühn, H. J. Schmitt
    Gemeinsame Stellungnahme der Fakultätentage Elektrotechnik und Informatik zur Abstimmung ihrer Fachgebierte im Bereich Informationstechnik. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1991, v:14, n:3, pp:163-167 [Journal]
  68. Reiner W. Hartenstein
    VLSI-Algorithmen - Das aktuelle Schlagwort. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1981, v:4, n:2, pp:124- [Journal]
  69. Reiner W. Hartenstein
    Silicon Compiler - Das aktuelle Schlagwort. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1983, v:6, n:4, pp:223-224 [Journal]
  70. Reiner W. Hartenstein
    Hardware/Software Co-Design - Das aktuelle Schlagwort [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1995, v:18, n:5, pp:286-287 [Journal]
  71. Reiner W. Hartenstein
    Custom Computing Machines - Das aktuelle Schlagwort [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1995, v:18, n:4, pp:228-229 [Journal]
  72. Reiner W. Hartenstein
    Suchlistenstrukturen zur Darstellung gerichteter Graphen und deren Anwendung bei Synthese und Minimierung spezieller endlicher Automaten. [Citation Graph (0, 0)][DBLP]
    Elektronische Rechenanlagen, 1970, v:12, n:4, pp:208-216 [Journal]
  73. Reiner W. Hartenstein
    VLSI-Bausteine in geringen Stückzahlen für Spezial-Anwendungen. [Citation Graph (0, 0)][DBLP]
    Elektronische Rechenanlagen, 1980, v:22, n:4, pp:159-173 [Journal]
  74. Jürgen Becker, Reiner W. Hartenstein
    Configware and morphware going mainstream. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:4-6, pp:127-142 [Journal]
  75. Mauricio Ayala-Rincón, Reiner W. Hartenstein, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos
    Architectural Specification, Exploration and Simulation Through Rewriting-Logic. [Citation Graph (0, 0)][DBLP]
    Revista Comlombiana de Computación, 2002, v:3, n:2, pp:- [Journal]
  76. Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
    Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:251-281 [Journal]
  77. Reiner W. Hartenstein
    KARL-II - eine Sprache zur Spezifikation beim Entwurf Kundenspezifischer Digitalbausteine. [Citation Graph (0, 0)][DBLP]
    Angewandte Informatik, 1982, v:24, n:12, pp:581-591 [Journal]
  78. Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
    From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]

  79. Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing. [Citation Graph (, )][DBLP]


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