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Ulrich Nageldinger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Universal Sequencer Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS, 1997, pp:143-152 [Conf]
  2. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
    A Synthesis System For Bus-Based Wavefront Array Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:274-283 [Conf]
  3. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Sequencer Hardware for Application Specific Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:392-401 [Conf]
  4. Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
    Parallelization in Co-Compilation for Configurable Accelerators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:23-33 [Conf]
  5. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:163-168 [Conf]
  6. Robert Fischer, Klaus Buchenrieder, Ulrich Nageldinger
    Reducing the Power Consumption of FPGAs through Retiming. [Citation Graph (0, 0)][DBLP]
    ECBS, 2005, pp:89-94 [Conf]
  7. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:222- [Conf]
  8. Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier
    Integration of Reconfigurable Hardware into System-Level Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:987-996 [Conf]
  9. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    Data scheduling to increase performance of parallel accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:294-303 [Conf]
  10. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:389-399 [Conf]
  11. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:189-198 [Conf]
  12. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    Mapping Applications onto Reconfigurable Kress Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:385-390 [Conf]
  13. Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann
    An Internet Based Development Framework for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:155-164 [Conf]
  14. Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
    An operating system for custom computing machines based on the Xputer paradigm. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:304-313 [Conf]
  15. Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber
    XMDS: The Xputer Multimedia Development System. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  16. Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber
    Interfacing the MoM-PDA to an Internet-based Development System. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  17. Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger
    A Low-Cost Realization of an Adaptable Protocol Processing Unit. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  18. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
    A Partitioning Programming Environment for a Novel Parallel Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:544-548 [Conf]
  19. Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
    On Reconfigurable Co-processing Units. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:67-72 [Conf]
  20. Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger
    Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:118-128 [Conf]
  21. Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier
    System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:115-121 [Conf]

  22. Generating MARTE Allocation Models from Activity Threads. [Citation Graph (, )][DBLP]


  23. Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). [Citation Graph (, )][DBLP]


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