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Peter Zipf: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Heiko Hinkelmann, Peter Zipf, Manfred Glesner
    A metric for the energy-efficiency of dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:152-161 [Conf]
  2. Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, A. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio
    CONAN - A Design Exploration Framework for Reliable Nano-Electronics. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:260-267 [Conf]
  3. Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
    Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:404-418 [Conf]
  4. Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
    Reconfigurable platforms for ubiquitous computing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:377-389 [Conf]
  5. Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner
    A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:632-637 [Conf]
  6. Stephan Bingemer, Peter Zipf, Manfred Glesner
    A granularity-based classification model for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:239- [Conf]
  7. Christine Bauer, Peter Zipf, Hans Wojtkowiak
    System Design with Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:250-259 [Conf]
  8. Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
    Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:381-390 [Conf]
  9. Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
    IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:526-535 [Conf]
  10. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
    Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1111-1114 [Conf]
  11. Mihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner
    The XPP Architecture and Its Co-simulation Within the Simulink Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:761-770 [Conf]
  12. Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
    A Framework for Teaching (Re)Configurable Architectures in Student Projects. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:444-451 [Conf]
  13. Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak
    Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:586-595 [Conf]
  14. Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner
    Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:329-334 [Conf]
  15. Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner
    A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:335-340 [Conf]
  16. Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner
    Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:448- [Conf]
  17. Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner
    Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:329-333 [Conf]
  18. Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner
    Dynamic power optimization of the trace-back process for the Viterbi algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:721-724 [Conf]
  19. Peter Zipf, Claude Stötzler, Manfred Glesner
    A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:266-267 [Conf]
  20. Peter Zipf, Claude Stötzler, Manfred Glesner
    Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:53-58 [Conf]
  21. Heiko Hinkelmann, Peter Zipf, Manfred Glesner
    A Concept for a Profile-based Dynamic Reconfiguration Mechanism. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:105-110 [Conf]
  22. Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
    Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:151-156 [Conf]
  23. Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
    Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:12-21 [Conf]
  24. Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner
    A switch architecture and signal synchronization for GALS system-on-chips. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:210-215 [Conf]
  25. Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner
    A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:44-49 [Conf]
  26. Stephan Bingemer, Peter Zipf, Manfred Glesner
    An Integrated Model Bridging the Gap between Technology and Economy. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:442-0 [Conf]
  27. Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner
    An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:167-0 [Conf]
  28. Heiko Hinkelmann, Peter Zipf, Manfred Glesner
    Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:436-441 [Conf]
  29. Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
    Multitasking Support for Dynamically Reconfig Urable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  30. Heiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner
    On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:185-191 [Conf]
  31. Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner
    A Customizable LEON2-Based VLIW Processor. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:55-60 [Conf]
  32. Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner
    Implementation of Realtime and Highspeed Phase Detector on FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:1-11 [Conf]
  33. Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
    Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:174-0 [Journal]

  34. Towards an Automated Design of Application-specific Reconfigurable Logic. [Citation Graph (, )][DBLP]

  35. A Power Estimation Model for an FPGA-based Softcore Processor. [Citation Graph (, )][DBLP]

  36. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]

  37. Application-specific reconfigurable processors. [Citation Graph (, )][DBLP]

  38. An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. [Citation Graph (, )][DBLP]

  39. Towards a unique FPGA-based identification circuit using process variations. [Citation Graph (, )][DBLP]

  40. Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. [Citation Graph (, )][DBLP]

  41. Generation of Synthetic Floating-Point benchmark circuits. [Citation Graph (, )][DBLP]

  42. Functional modeling techniques for a wireless LAN OFDM transceiver. [Citation Graph (, )][DBLP]

  43. Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. [Citation Graph (, )][DBLP]

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