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Michael Hübner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker
    Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:39-44 [Conf]
  2. Matthias Riebisch, Michael Hübner
    Traceability-Driven Model Refinement for Test Case Generation. [Citation Graph (0, 0)][DBLP]
    ECBS, 2005, pp:113-120 [Conf]
  3. Brandon Blodget, Christophe Bobda, Michael Hübner, Adronis Niyonkuru
    Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:801-810 [Conf]
  4. Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker
    Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1037-1041 [Conf]
  5. Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
    On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:454-463 [Conf]
  6. Michael Hübner, Katarina Paulsson, Jürgen Becker
    Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  7. Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
    An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  8. M. Hübner, C. Schuck, J. Becker
    Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker
    Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:159-166 [Conf]
  10. Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker
    New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:97-102 [Conf]
  11. Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
    Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:41-46 [Conf]
  12. Alisson V. De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher
    Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:35-40 [Conf]
  13. Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas
    Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:35-42 [Conf]
  14. J. Becker, M. Hübner
    Run-time reconfigurabilility and other future trends. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:9-11 [Conf]
  15. M. Hübner, J. Becker
    Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:1-4 [Conf]
  16. Katarina Paulsson, Michael Hübner, Jürgen Becker
    On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:173-178 [Conf]
  17. Michael Hübner, Tobias Becker, Jürgen Becker
    Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:28-32 [Conf]
  18. Jürgen Becker, Michael Hübner, Michael Ullmann
    Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:283-288 [Conf]
  19. Jürgen Becker, Michael Hübner, Michael Ullmann
    Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:129-0 [Conf]
  20. Katarina Paulsson, Michael Hübner, Jürgen Becker
    Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:288-291 [Conf]
  21. Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker
    Communication Architectures for Dynamically Reconfigurable FPGA Designs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  22. Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker
    Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:1-6 [Conf]

  23. Physical 2D Morphware and Power Reduction Methods for Everyone. [Citation Graph (, )][DBLP]


  24. Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. [Citation Graph (, )][DBLP]


  25. Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. [Citation Graph (, )][DBLP]


  26. Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. [Citation Graph (, )][DBLP]


  27. High Performance Architectures and Compilers. [Citation Graph (, )][DBLP]


  28. A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  29. Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. [Citation Graph (, )][DBLP]


  30. On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. [Citation Graph (, )][DBLP]


  31. Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. [Citation Graph (, )][DBLP]


  32. Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. [Citation Graph (, )][DBLP]


  33. New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. [Citation Graph (, )][DBLP]


  34. A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. [Citation Graph (, )][DBLP]


  35. Data path driven waveform-like reconfiguration. [Citation Graph (, )][DBLP]


  36. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  37. Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. [Citation Graph (, )][DBLP]


  38. Dynamic reconfigurable mixed-signal architecture for safety critical applications. [Citation Graph (, )][DBLP]


  39. Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. [Citation Graph (, )][DBLP]


  40. Runtime adaptive multi-processor system-on-chip: RAMPSoC. [Citation Graph (, )][DBLP]


  41. A framework for dynamic 2D placement on FPGAs. [Citation Graph (, )][DBLP]


  42. Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. [Citation Graph (, )][DBLP]


  43. Towards Novel Approaches in Design Automation for FPGA Power Optimization. [Citation Graph (, )][DBLP]


  44. BRICK: a multi-context expression grained reconfigurable architecture. [Citation Graph (, )][DBLP]


  45. New tool support and architectures in adaptive reconfigurable computing. [Citation Graph (, )][DBLP]


  46. FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. [Citation Graph (, )][DBLP]


  47. Data reallocation by exploiting FPGA configuration mechanisms. [Citation Graph (, )][DBLP]


  48. An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. [Citation Graph (, )][DBLP]


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