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Heinrich Theodor Vierhaus: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christian Galke, René Kothe, Heinrich Theodor Vierhaus
    Logic Self Repair. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:36-44 [Conf]
  2. Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
    Local microcode generation in system design. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:171-187 [Conf]
  3. U. Krautz, Matthias Pflanz, Christian Jacobi 0002, H. W. Tast, Kai Weber, Heinrich Theodor Vierhaus
    Evaluating coverage of error detection logic for soft errors using formal methods. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:176-181 [Conf]
  4. C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus
    A register-transfer-level fault simulator for permanent and transient faults in embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:811- [Conf]
  5. René Kothe, Christian Galke, S. Schultke, H. Froeschke, S. Gaede, Heinrich Theodor Vierhaus
    Hardware/Software Based Hierarchical Self Test for SoCs. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:159-160 [Conf]
  6. René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube
    Embedded Self Repair by Transistor and Gate Level Reconfiguration. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:210-215 [Conf]
  7. René Kothe, Heinrich Theodor Vierhaus
    Flip-Flops and Scan-Path Elements for Nanoelectronics. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:307-312 [Conf]
  8. Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber
    A Mixed Language Fault Simulation of VHDL and SystemC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:275-279 [Conf]
  9. Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus
    Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:433-438 [Conf]
  10. Heinrich Theodor Vierhaus, Helmut Rossmann
    Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:339-343 [Conf]
  11. H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
    An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:112-117 [Conf]
  12. Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus
    A Design Exploration Environment. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:77-80 [Conf]
  13. Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold
    Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:36-39 [Conf]
  14. Uwe Hübner, Heinrich Theodor Vierhaus
    Efficient partitioning and analysis of digital CMOS-circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:280-283 [Conf]
  15. Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
    A Test Processor Concept for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:210-0 [Conf]
  16. Ursula Westerholz, Heinrich Theodor Vierhaus
    Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:472-475 [Conf]
  17. R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus
    Testability Analysis for Test Generation in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:350-353 [Conf]
  18. Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus
    A Hierarchical Self Test Scheme for SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:37-44 [Conf]
  19. Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus
    Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:183-0 [Conf]
  20. Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
    On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:178- [Conf]
  21. Matthias Pflanz, Heinrich Theodor Vierhaus
    Control Signal Protection For High Performance Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:173-0 [Conf]
  22. Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus
    On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:69-73 [Conf]
  23. Matthias Pflanz, K. Walther, Heinrich Theodor Vierhaus
    On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:51-53 [Conf]
  24. René Kothe, Christian Galke, Heinrich Theodor Vierhaus
    A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:241-246 [Conf]
  25. S. Habermann, René Kothe, Heinrich Theodor Vierhaus
    Built-in Self Repair by Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:187-188 [Conf]
  26. Christian Galke, René Kothe, S. Schultke, K. Winkler, J. Honko, Heinrich Theodor Vierhaus
    Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:181-182 [Conf]
  27. Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus
    Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:21-29 [Conf]
  28. Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch
    An efficient on-line-test and back-up scheme for embedded processors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:964-972 [Conf]
  29. Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser
    CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:83-91 [Conf]
  30. H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
    A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    PARCO, 1997, pp:549-556 [Conf]
  31. Silvio Misera, Heinrich Theodor Vierhaus
    FIT - A Parallel Hierarchical Fault Simulation Environment. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:289-294 [Conf]
  32. H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
    Automatic Test Pattern Generation with Optimal Load Balancing. [Citation Graph (0, 0)][DBLP]
    PVM, 1996, pp:205-212 [Conf]
  33. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus
    Improving topological ATPG with symbolic techniques. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:338-343 [Conf]
  34. Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich Theodor Vierhaus, Pawel Wlaz
    Synchronization Fault Cryptanalysis for Breaking A5/1. [Citation Graph (0, 0)][DBLP]
    WEA, 2005, pp:415-427 [Conf]
  35. Matthias Pflanz, Heinrich Theodor Vierhaus
    Online Check and Recovery Techniques for Dependable Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:5, pp:24-40 [Journal]
  36. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
    SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:191-202 [Journal]
  37. Uwe Gläser, Heinrich Theodor Vierhaus
    Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:4, pp:410-423 [Journal]
  38. Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano
    Partitioning and analysis of static digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1292-1310 [Journal]
  39. R. Frost Brandenburg, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus
    A Configurable Modular Test Processor and Scan Controller Architecture. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:277-284 [Conf]

  40. A scheme of logic self repair including local interconnects. [Citation Graph (, )][DBLP]


  41. Fault Injection Techniques and their Accelerated Simulation in SystemC. [Citation Graph (, )][DBLP]


  42. Timing- / Power-Optimization for Digital Logic Based on Standard Cells. [Citation Graph (, )][DBLP]


  43. Embedded Diagnostic Logic Test Exploiting Regularity. [Citation Graph (, )][DBLP]


  44. A Concept for Logic Self Repair. [Citation Graph (, )][DBLP]


  45. Reliability Estimation Process. [Citation Graph (, )][DBLP]


  46. FOGBUSTER: an efficient algorithm for sequential test generation. [Citation Graph (, )][DBLP]


  47. Basic Architecture for Logic Self Repair. [Citation Graph (, )][DBLP]


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