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Lech Józwiak: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lech Józwiak
    Life-Inspired Systems and Their Quality-Driven Design. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:1-16 [Conf]
  2. Lech Józwiak, Artur Chojnacki
    High-quality sub-function construction in functional decomposition based on information relationship measures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:383-390 [Conf]
  3. Lech Józwiak, Szymon Bieganski
    High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:450-459 [Conf]
  4. Lech Józwiak
    Life-Inspired Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:36-43 [Conf]
  5. Lech Józwiak, Szymon Bieganski
    Information Trans-Coders in Information-Driven Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:288-397 [Conf]
  6. Lech Józwiak, Szymon Bieganski, Artur Chojnacki
    Information-driven Library-based Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:148-157 [Conf]
  7. Lech Józwiak, Artur Chojnacki
    Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:30-37 [Conf]
  8. Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
    Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:46-53 [Conf]
  9. Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
    An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:160-167 [Conf]
  10. Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
    Regular Realization of Symmetric Functions Using Reversible Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:245-253 [Conf]
  11. Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski
    Multi-objective Optimal FSM State Assignment. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:385-396 [Conf]
  12. Lech Józwiak, Sien-An Ong
    Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:397-406 [Conf]
  13. Song Chen, Adam Postula, Lech Józwiak
    Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1170-1177 [Conf]
  14. Michael Burns, Marek A. Perkowski, Lech Józwiak
    An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10016-10023 [Conf]
  15. Lech Józwiak
    Information Relationships and Measures An Analysis Apparatus for Efficient Information System Synthesis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:13-23 [Conf]
  16. Lech Józwiak
    On the use of term trees for effective and efficient test pattern generation. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:87-95 [Conf]
  17. Lech Józwiak
    Digital System Design: Architectures, Methods and Tools. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1004-0 [Conf]
  18. Lech Józwiak, Artur Chojnacki
    Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1150-1160 [Conf]
  19. Lech Józwiak, Niek Ederveen, Adam Postula
    Solving Synthesis Problems with Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10001-10007 [Conf]
  20. Lech Józwiak, Sien-An Ong
    Quality-Driven Decision Making Methodology for System-Level Design. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:8-18 [Conf]
  21. Lech Józwiak, Aleksander Slusarczyk
    A New State Assignment Method Targeting FPGA Implementations. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1050-1059 [Conf]
  22. Sanof Mohamed, Marek A. Perkowski, Lech Józwiak
    Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:31-0 [Conf]
  23. Torrey Lewis, Marek A. Perkowski, Lech Józwiak
    Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1326-1334 [Conf]
  24. Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak
    Design of Self-Synchronized Component FSMs for Self-Timed Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10253-10260 [Conf]
  25. Sien-An Ong, Kari Tiensyrjä, Lech Józwiak
    Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:172-181 [Conf]
  26. Adam Postula, Song Chen, Lech Józwiak, David Abramson
    Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10115-10122 [Conf]
  27. Mariusz Rawski, Lech Józwiak, Tadeusz Luba
    The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1086-1093 [Conf]
  28. Mariusz Rawski, Lech Józwiak, Tadeusz Luba
    Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1094-1101 [Conf]
  29. Mariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki
    Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10008-10015 [Conf]
  30. Rafal Rzechowski, Tadeusz Luba, Lech Józwiak
    Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1368-1375 [Conf]
  31. Lech Józwiak, Adam Postula
    Genetic Engineering versus Natural Evolution Genetic Algorithms with Deterministic Operators. [Citation Graph (0, 0)][DBLP]
    IC-AI, 1999, pp:58-64 [Conf]
  32. Artur Chojnacki, Lech Józwiak
    Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:83-90 [Conf]
  33. Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak
    Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:287-292 [Conf]
  34. Lech Józwiak
    Information Relationships and Measures in Application to Logic Design. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:228-235 [Conf]
  35. Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang
    Decomposition of Multiple-Valued Relations . [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:13-18 [Conf]
  36. Artur Chojnacki, Lech Józwiak
    High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:409-414 [Conf]
  37. Lech Józwiak
    Quality-Driven System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:93-0 [Conf]
  38. Lech Józwiak, Kaustav Banerjee
    Plenary Session 2P. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:461- [Conf]
  39. Aleksander Slusarczyk, Lech Józwiak
    Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:87-0 [Conf]
  40. Lech Józwiak
    Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:6- [Conf]
  41. Srikanth Venkataraman, Nagesh Nagapalli, Lech Jozwiak
    Quality Driven Manufacturing and SOC Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:5- [Conf]
  42. Lech Józwiak
    Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:139-142 [Conf]
  43. Lech Józwiak
    Analysis and Synthesis of Information Systems with Information Relationships and Measures. [Citation Graph (0, 0)][DBLP]
    Rough Sets and Current Trends in Computing, 1998, pp:585-588 [Conf]
  44. Mariusz Rawski, Lech Józwiak, Artur Chojnacki
    Application of the Information Measures to Input Support Selection in Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    Rough Sets and Current Trends in Computing, 1998, pp:573-580 [Conf]
  45. Lech Józwiak
    Advanced AI Search Techniques in Modern Digital Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    Artif. Intell. Rev., 2003, v:20, n:3-4, pp:269-318 [Journal]
  46. Henry Selvaraj, Lech Józwiak
    Reconfigurable embedded systems: Synthesis, design and application. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:6-7, pp:347-349 [Journal]
  47. Lech Józwiak, Szymon Bieganski, Artur Chojnacki
    Information-driven circuit synthesis with the pre-characterized gate libraries. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:6-7, pp:405-423 [Journal]
  48. Lech Józwiak, Aleksander Slusarczyk
    General decomposition of incompletely specified sequential machines with multi-state behavior realization. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:8, pp:445-492 [Journal]
  49. Martyn Edwards, Lech Józwiak
    Preface. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:485-487 [Journal]
  50. Lech Józwiak, Aleksander Slusarczyk, Artur Chojnacki
    Fast and compact sequential circuits for the FPGA-based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:4-6, pp:227-246 [Journal]
  51. Lech Józwiak, Artur Chojnacki
    Effective and efficient FPGA synthesis through general functional decomposition. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:4-6, pp:247-265 [Journal]
  52. Martyn Edwards, Lech Józwiak
    Special-issue on reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:4-6, pp:123-125 [Journal]
  53. Lech Józwiak, Adam Postula
    Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:1-3, pp:99-112 [Journal]
  54. Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak
    Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:3, pp:41-51 [Journal]
  55. Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak
    Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:3, pp:52-61 [Journal]
  56. Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
    Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:177-184 [Conf]

  57. Technology Library Modelling for Information-driven Circuit Synthesis. [Citation Graph (, )][DBLP]


  58. Efficent suboptimal state assignment for large sequential machines. [Citation Graph (, )][DBLP]


  59. High-Quality Circuit Synthesis for Modern Technologies. [Citation Graph (, )][DBLP]


  60. Quality-driven methodology for demanding accelerator design. [Citation Graph (, )][DBLP]


  61. Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. [Citation Graph (, )][DBLP]


  62. Architecture Design of Reconfigurable Accelerators for Demanding Applications. [Citation Graph (, )][DBLP]


  63. CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. [Citation Graph (, )][DBLP]


  64. Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. [Citation Graph (, )][DBLP]


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