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Mario Porrmann: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Heiko Kalte, Mario Porrmann, Ulrich Rückert
    Leistungsbewertung unterschiedlicher Einbettungsvariaten dynamisch rekonfigurierbarer Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:235-244 [Conf]
  2. Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert
    GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:268-282 [Conf]
  3. Jörg-Christian Niemann, Christian Liß, Mario Porrmann, Ulrich Rückert
    A Multiprocessor Cache for Massively Parallel SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:83-97 [Conf]
  4. Heiko Kalte, Mario Porrmann
    REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:403-412 [Conf]
  5. Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
    A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:758-763 [Conf]
  6. Heiko Kalte, Markus Koester, Boris Kettelhoit, Mario Porrmann, Ulrich Rückert
    A Comparative Study on System Approaches for Partially Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:70-76 [Conf]
  7. Markus Koester, Heiko Kalte, Mario Porrmann
    Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:70-76 [Conf]
  8. Mario Porrmann, Marc Franzmeier, Heiko Kalte, Ulf Witkowski, Ulrich Rückert
    A reconfigurable SOM hardware accelerator. [Citation Graph (0, 0)][DBLP]
    ESANN, 2002, pp:337-342 [Conf]
  9. Mario Porrmann, Ulrich Rückert, Karl Michael Marks, Jörg Landmann
    HiBRIC-MEM, a Memory Controller for PowerPC Based Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:653-657 [Conf]
  10. Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert
    Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:842-846 [Conf]
  11. Heiko Kalte, Mario Porrmann
    Context Saving and Restoring for Multitasking in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:223-228 [Conf]
  12. Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert
    Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1048-1057 [Conf]
  13. Markus Koester, Mario Porrmann, Heiko Kalte
    Task Placement for Heterogeneous Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:43-50 [Conf]
  14. Carlos Paiz, Christopher Pohl, Mario Porrmann
    Reconfigurable hardware in-the-loop simulations for digital control design. [Citation Graph (0, 0)][DBLP]
    ICINCO-SPSMC, 2006, pp:39-46 [Conf]
  15. Heiko Kalte, Gareth Lee, Mario Porrmann, Ulrich Rückert
    REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  16. Heiko Kalte, Mario Porrmann, Ulrich Rückert
    System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  17. Markus Koester, Mario Porrmann, Ulrich Rückert
    Placement-Oriented Modeling of Partially Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  18. J. Hagemeyer, Boris Kettelhoit, Mario Porrmann
    Dedicated module access in dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  19. Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
    A Scalable Parallel SoC Architecture for Network Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:311-313 [Conf]
  20. Stefan Rüping, Mario Porrmann, Ulrich Rückert
    A High Performance SOFM Hardware-System. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:772-781 [Conf]
  21. Olaf Bonorden, Nikolaus Brüls, Uwe Kastens, Dinh Khoi Le, Friedhelm Meyer auf der Heide, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert, Adrian Slowik, Michael Thies
    A holistic methodology for network processor design. [Citation Graph (0, 0)][DBLP]
    LCN, 2003, pp:583-0 [Conf]
  22. Marc Franzmeier, Christopher Pohl, Mario Porrmann, Ulrich Rückert
    Hardware Accelerated Data Analysis. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:309-314 [Conf]
  23. Matthias Grünewald, Dinh Khoi Le, Uwe Kastens, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert, Adrian Slowik, Michael Thies
    Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:209-214 [Conf]
  24. Christian Sauer, Matthias Gries, J.-C. Niemann, M. Porrmann, M. Thies
    Application-Driven Development of Concurrent Packet Processing Platforms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:55-61 [Conf]
  25. Erik Vonnahme, Björn Griese, Mario Porrmann, Ulrich Rückert
    Dynamic Reconfiguration of Real-Time Network Interfaces. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:376-379 [Conf]
  26. Björn Griese, Boris Kettelhoit, Mario Porrmann
    Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:214-219 [Conf]
  27. Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert
    Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:243-0 [Conf]
  28. Heiko Kalte, Mario Porrmann, Ulrich Rückert
    Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  29. Stefan Rüping, Mario Porrmann, Ulrich Rückert
    SOM accelerator system. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1998, v:21, n:1-3, pp:31-50 [Journal]
  30. Boris Kettelhoit, Mario Porrmann
    A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  31. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert
    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  32. Carlos Paiz, Boris Kettelhoit, Mario Porrmann
    A design framework for FPGA-based dynamically reconfigurable digital controllers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3708-3711 [Conf]
  33. Bjørn Jager, Mario Porrmann, Ulrich Rückert
    Bio-inspired massively parallel architectures for nanotechnologies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  34. Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert
    Defragmentation Algorithms for Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:41-53 [Conf]
  35. Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert
    Resource efficiency of the GigaNetIC chip multiprocessor architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:285-299 [Journal]

  36. Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]


  37. Design optimizations to improve placeability of partial reconfiguration modules. [Citation Graph (, )][DBLP]


  38. GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. [Citation Graph (, )][DBLP]


  39. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  40. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. [Citation Graph (, )][DBLP]


  41. Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. [Citation Graph (, )][DBLP]


  42. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  43. SelfS - A real-time protocol for virtual ring topologies. [Citation Graph (, )][DBLP]


  44. Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]


  45. A Synchronization Method for Register Traces of Pipelined Processors. [Citation Graph (, )][DBLP]


  46. A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems. [Citation Graph (, )][DBLP]


  47. Design Space Exploration for Memory Subsystems of VLIW Architectures. [Citation Graph (, )][DBLP]


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