SCEAS

The SCEAS System

Search the dblp DataBase

Title:
Author:

Stefanos Kaxiras: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Georgios Keramidas, Konstantinos Aisopos, Stefanos Kaxiras
Dynamic Dictionary-Based Data Compression for Level-1 Caches. [Citation Graph (0, 0)][DBLP]
ARCS, 2006, pp:114-129 [Conf]
Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads. [Citation Graph (0, 0)][DBLP]
CASES, 2001, pp:211-220 [Conf]
Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. [Citation Graph (0, 0)][DBLP]
Conf. Computing Frontiers, 2007, pp:113-122 [Conf]
Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner
Topic 18: Embedded Parallel Systems. [Citation Graph (0, 0)][DBLP]
Euro-Par, 2006, pp:1179- [Conf]
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
TCP: Tag Correlating Prefetchers. [Citation Graph (0, 0)][DBLP]
HPCA, 2003, pp:317-326 [Conf]
Stefanos Kaxiras, James R. Goodman
Improving CC-NUMA Performance Using Instruction-Based Prediction. [Citation Graph (0, 0)][DBLP]
HPCA, 1999, pp:161-0 [Conf]
Stefanos Kaxiras, Cliff Young
Coherence Communication Prediction in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:156-167 [Conf]
Stefanos Kaxiras, James R. Goodman
The GLOW Cache Coherence Protocol Extensions for Widely Shared Data. [Citation Graph (0, 0)][DBLP]
International Conference on Supercomputing, 1996, pp:35-43 [Conf]
Stefanos Kaxiras, Stein Gjessing, James R. Goodman
A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
International Conference on Supercomputing, 1998, pp:457-464 [Conf]
Stefanos Kaxiras, Georgios Keramidas
IPStash: a set-associative memory approach for efficient IP-lookup. [Citation Graph (0, 0)][DBLP]
INFOCOM, 2005, pp:992-1001 [Conf]
Stefanos Kaxiras
Kiloprocessor Extensions to SCI. [Citation Graph (0, 0)][DBLP]
IPPS, 1996, pp:166-172 [Conf]
Doug Burger, Stefanos Kaxiras, James R. Goodman
DataScalar Architectures. [Citation Graph (0, 0)][DBLP]
ISCA, 1997, pp:338-349 [Conf]
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. [Citation Graph (0, 0)][DBLP]
ISCA, 2002, pp:209-220 [Conf]
Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi
Cache decay: exploiting generational behavior to reduce cache leakage power. [Citation Graph (0, 0)][DBLP]
ISCA, 2001, pp:240-251 [Conf]
Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
Managing leakage for transient data: decay and quasi-static 4T memory cells. [Citation Graph (0, 0)][DBLP]
ISLPED, 2002, pp:52-55 [Conf]
Stefanos Kaxiras, Polychronis Xekalakis
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. [Citation Graph (0, 0)][DBLP]
ISLPED, 2004, pp:108-113 [Conf]
Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas
A simple mechanism to adapt leakage-control policies to temperature. [Citation Graph (0, 0)][DBLP]
ISLPED, 2005, pp:54-59 [Conf]
Stefanos Kaxiras, Georgios Keramidas
IPStash: a Power-Efficient Memory Architecture for IP-lookup. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:361-372 [Conf]
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. [Citation Graph (0, 0)][DBLP]
PACS, 2000, pp:82-96 [Conf]
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos
Preventing Denial-of-Service Attacks in Shared CMP Caches. [Citation Graph (0, 0)][DBLP]
SAMOS, 2006, pp:359-372 [Conf]
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Zhigang Hu, Margaret Martonosi, Douglas W. Clark
Implementing Decay Techniques using 4T Quasi-Static Memory Cells. [Citation Graph (0, 0)][DBLP]
Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras
Implementing branch-predictor decay using quasi-static memory cells. [Citation Graph (0, 0)][DBLP]
TACO, 2004, v:1, n:2, pp:180-219 [Journal]
Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
Let caches decay: reducing leakage energy via exploitation of cache generational behavior. [Citation Graph (0, 0)][DBLP]
ACM Trans. Comput. Syst., 2002, v:20, n:2, pp:161-190 [Journal]
Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras
Applying Decay to Reduce Dynamic Power in Set-Associative Caches. [Citation Graph (0, 0)][DBLP]
HiPEAC, 2007, pp:38-53 [Conf]
Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten
Modeling Cache Sharing on Chip Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
IISWC, 2006, pp:160-171 [Conf]
MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance. [Citation Graph (, )][DBLP]
Where replacement algorithms fail: a thorough analysis. [Citation Graph (, )][DBLP]
Low power microarchitecture with instruction reuse. [Citation Graph (, )][DBLP]
Interval-based models for run-time DVFS orchestration in superscalar processors. [Citation Graph (, )][DBLP]
Instruction Precomputation for Fault Detection. [Citation Graph (, )][DBLP]
Cache replacement based on reuse-distance prediction. [Citation Graph (, )][DBLP]
Efficient microarchitecture policies for accurately adapting to power constraints. [Citation Graph (, )][DBLP]
Instruction-based reuse-distance prediction for effective cache management. [Citation Graph (, )][DBLP]

Search in 0.005secs, Finished in 0.007secs

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades

NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP