The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Mladen Berekovic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Helge Kloos, Mladen Berekovic, Peter Pirsch
    Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. [Citation Graph (0, 0)][DBLP]
    ARCS, 1999, pp:5-14 [Conf]
  2. Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo
    Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:15-24 [Conf]
  3. Mladen Berekovic, Peter Pirsch
    An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. [Citation Graph (0, 0)][DBLP]
    Computer Graphics International, 1998, pp:411-0 [Conf]
  4. Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch
    Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:56-61 [Conf]
  5. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch
    HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20008-20013 [Conf]
  6. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch
    HiBRID-SoC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:101-104 [Conf]
  7. Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, H. Runge
    Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. [Citation Graph (0, 0)][DBLP]
    ICME, 2001, pp:- [Conf]
  8. Mladen Berekovic, K. Jacob, Peter Pirsch
    Architecture of a hardware module for MPEG-4 shape decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:157-160 [Conf]
  9. Mladen Berekovic, Tim Niggemeier
    A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:289-298 [Conf]
  10. Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels
    Coprocessor architecture for MPEG-4 video object rendering. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:1451-1458 [Conf]
  11. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch
    HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:155-160 [Conf]
  12. Mladen Berekovic, Sören Moch, Peter Pirsch
    A scalable, clustered SMT processor for digital signal processing. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:62-69 [Journal]
  13. Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, A. Dehnhardt, Peter Pirsch
    HIBRID-SOC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:55-61 [Journal]
  14. Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch
    Multicore system-on-chip architecture for MPEG-4 streaming video. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:8, pp:688-0 [Journal]
  15. C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet
    Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:177-182 [Conf]
  16. Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen
    Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:385-395 [Conf]
  17. Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic
    MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:26-38 [Conf]
  18. Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev
    Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:1-13 [Conf]
  19. Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Suk Jin Kim
    Hardware and a Tool Chain for ADRES. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:425-430 [Conf]

  20. Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. [Citation Graph (, )][DBLP]


  21. Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. [Citation Graph (, )][DBLP]


  22. Low power microarchitecture with instruction reuse. [Citation Graph (, )][DBLP]


  23. Electrocardiogram on Wireless Sensor Nodes. [Citation Graph (, )][DBLP]


  24. A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. [Citation Graph (, )][DBLP]


  25. Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring. [Citation Graph (, )][DBLP]


  26. Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. [Citation Graph (, )][DBLP]


  27. Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (, )][DBLP]


  28. Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. [Citation Graph (, )][DBLP]


  29. Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization. [Citation Graph (, )][DBLP]


  30. Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.304secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002