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Peter M. Kogge: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter M. Kogge
    Declarative Computing: A Technology Driver. [Citation Graph (0, 0)][DBLP]
    ARCS, 1992, pp:1-17 [Conf]
  2. Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter
    Combined DRAM and logic chip for massively parallel systems. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:4-16 [Conf]
  3. Lilia Yerosheva, Peter M. Kogge
    Prototyping Execution Models for HTMT Petaflop Machine in Java. [Citation Graph (0, 0)][DBLP]
    CANPC, 1999, pp:32-46 [Conf]
  4. Craig S. Lent, Sarah E. Frost, Peter M. Kogge
    Reversible computation with quantum-dot cellular automata (QCA). [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:403- [Conf]
  5. Sarah E. Murphy, Erik DeBenedictis, Peter M. Kogge
    General floorplan for reversible quantum-dot cellular automata. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:77-82 [Conf]
  6. Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Jay B. Brockman, Ron Brightwell, Keith D. Underwood
    Implications of a PIM Architectural Model for MPI. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2003, pp:259-0 [Conf]
  7. Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier
    Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:363-368 [Conf]
  8. Michael T. Niemier, Michael J. Kontz, Peter M. Kogge
    A design of and design tools for a novel quantum dot based microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:227-232 [Conf]
  9. Kanad Ghose, Kiran Raghavendra Desai, Peter M. Kogge
    Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:441-0 [Conf]
  10. Michael T. Niemier, Peter M. Kogge
    Logic in Wire: Using Quantum Dots to Implement a Microprocessor. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:118-121 [Conf]
  11. Peter M. Kogge
    The State of State. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:266-0 [Conf]
  12. Michael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge
    Using Circuits and Systems-Level Research to Drive Nanotechnology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:302-309 [Conf]
  13. Peter M. Kogge
    EXECUBE - A New Architecture for Scalable MPPs. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:77-84 [Conf]
  14. Jay B. Brockman, Peter M. Kogge, Thomas L. Sterling, Vincent W. Freeh, Shannon K. Kuntz
    Microservers: a new memory semantics for massively parallel computing. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:454-463 [Conf]
  15. Richard C. Murphy, Arun Rodrigues, Peter M. Kogge, Keith D. Underwood
    The implications of working set analysis on supercomputing memory hierarchy design. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:332-340 [Conf]
  16. Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood
    Characterizing a new class of threads in scientific applications for high end supercomputers. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:164-174 [Conf]
  17. Richard C. Murphy, Peter M. Kogge, Arun Rodrigues
    The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:85-103 [Conf]
  18. Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge
    Optimizing Data Scheduling on Processor-in-Memory Arrays. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:57-61 [Conf]
  19. Lilia Yerosheva, Shannon K. Kuntz, Peter M. Kogge, Jay B. Brockman
    A Microserver View of HTMT. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:3- [Conf]
  20. Peter M. Kogge
    Maximal Rate Pipelined Solutions to Recurrance Problems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:71-76 [Conf]
  21. Peter M. Kogge
    The Microprogramming of Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1977, pp:63-70 [Conf]
  22. Michael T. Niemier, Peter M. Kogge
    Exploring and exploiting wire-level pipelining in emerging technologies. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:166-177 [Conf]
  23. Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge
    Energy: efficient instruction dispatch buffer design for superscalar processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:237-242 [Conf]
  24. Victor V. Zyuban, Peter M. Kogge
    Optimization of high-performance superscalar architectures for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:84-89 [Conf]
  25. Victor V. Zyuban, Peter M. Kogge
    The energy complexity of register files. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:305-310 [Conf]
  26. Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge
    Cache implications of aggressively pipelined high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:123-132 [Conf]
  27. Sarah E. Frost, Arun Rodrigues, Charles A. Giefer, Peter M. Kogge
    Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:19-28 [Conf]
  28. Michael T. Niemier, Peter M. Kogge
    The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:3-10 [Conf]
  29. Alexei Kudriavtsev, Peter M. Kogge
    Generation of permutations for SIMD processors. [Citation Graph (0, 0)][DBLP]
    LCTES, 2005, pp:147-156 [Conf]
  30. Gary H. Bernstein, Jay B. Brockman, Peter M. Kogge, Gregory L. Snider, Barbara E. Walvoord
    From Bits to Chips: A Multidisciplinary Curriculum for Microelectronics System Design Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:95-97 [Conf]
  31. James F. Kramer, Matthias Scheutz, Jay B. Brockman, Peter M. Kogge
    Facing up to the Inevitable: Intelligent Error Recovery in Massively Parallel Processing in Memory Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:227-233 [Conf]
  32. Shannon K. Kuntz, Richard C. Murphy, Michael T. Niemier, Jesús A. Izaguirre, Peter M. Kogge
    Petaflop Computing for Protein Folding. [Citation Graph (0, 0)][DBLP]
    PPSC, 2001, pp:- [Conf]
  33. Erik DeBenedictis, David E. Keyes, Peter M. Kogge
    M06 - Issues for the future of supercomputing: impact of Moore's law and architecture on application performance. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:220- [Conf]
  34. Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood
    Poster reception - The structural simulation toolkit: exploring novel architectures. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:157- [Conf]
  35. Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp, David E. Keyes, Pete Beckman
    Multi-core issues - Multi-Core for HPC: breakthrough or breakdown? [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:73- [Conf]
  36. Danny Z. Chen, Ovidiu Daescu, John Hershberger, Peter M. Kogge, Jack Snoeyink
    Polygonal path approximation with angle constraints. [Citation Graph (0, 0)][DBLP]
    SODA, 2001, pp:342-343 [Conf]
  37. Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge
    A low cost, multithreaded processing-in-memory system. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:16-22 [Conf]
  38. Danny Z. Chen, Ovidiu Daescu, John Hershberger, Peter M. Kogge, Ningfang Mi, Jack Snoeyink
    Polygonal path simplification with angle constraints. [Citation Graph (0, 0)][DBLP]
    Comput. Geom., 2005, v:32, n:3, pp:173-187 [Journal]
  39. Peter M. Kogge
    Am Architectural Trail to Threaded-Code Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1982, v:15, n:3, pp:22-32 [Journal]
  40. Peter M. Kogge
    Parallel Solution of Recurrence Problems. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1974, v:18, n:2, pp:138-148 [Journal]
  41. Peter M. Kogge
    Function-based computing and parallelism: A review. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1985, v:2, n:3, pp:243-253 [Journal]
  42. Victor V. Zyuban, Peter M. Kogge
    Inherently Lower-Power High-Performance Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:268-285 [Journal]
  43. Richard C. Murphy, Peter M. Kogge
    On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:7, pp:937-945 [Journal]
  44. Arun Rodrigues, Kyle Wheeler, Peter M. Kogge, Keith D. Underwood
    Fine-Grained Message Pipelining for Improved MPI Performance. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2006, pp:- [Conf]
  45. Sheng Li, Amit Kashyap, Shannon K. Kuntz, Jay B. Brockman, Peter M. Kogge, Paul L. Springer, Gary Block
    A Heterogeneous Lightweight Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  46. Srinivas Sridharan, Arun Rodrigues, Peter M. Kogge
    Evaluating synchronization techniques for light-weight multithreaded/multicore architectures. [Citation Graph (0, 0)][DBLP]
    SPAA, 2007, pp:57-58 [Conf]
  47. Victor V. Zyuban, Peter M. Kogge
    Application of STD to latch-power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:111-115 [Journal]
  48. Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter M. Kogge
    Energy-efficient issue queue design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:789-800 [Journal]

  49. Models for generating locality-tuned traveling threads for a hierarchical multi-level heterogeneous multicore. [Citation Graph (, )][DBLP]

  50. Design of a mask-programmable memory/multiplier array using G4-FET technology. [Citation Graph (, )][DBLP]

  51. Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder. [Citation Graph (, )][DBLP]

  52. System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata. [Citation Graph (, )][DBLP]

  53. Memory model effects on application performance for a lightweight multithreaded architecture. [Citation Graph (, )][DBLP]

  54. The Challenges of Petascale Architectures. [Citation Graph (, )][DBLP]

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