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Oliver Bringmann: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
    Towards a Framework and a Design Methodology for Autonomous SoC. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:101-108 [Conf]
  2. Oliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn
    Conflict analysis in multiprocess synthesis for optimized system integration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:15-20 [Conf]
  3. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Worst-case performance analysis of parallel, communicating software processes. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:37-42 [Conf]
  4. Wolfgang Klingauf, Robert Günzel, Oliver Bringmann, Pavel Parfuntseu, Mark Burton
    GreenBus: a generic interconnect fabric for transaction level modelling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:905-910 [Conf]
  5. Oliver Bringmann, Wolfgang Rosenstiel
    Cross-Level Hierarchical High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:451-456 [Conf]
  6. Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn
    Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:326-332 [Conf]
  7. Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel
    Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:792-797 [Conf]
  8. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Communication Analysis for System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:648-655 [Conf]
  9. Alexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel
    Formal performance analysis and simulation of UML/SysML models for ESL design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:242-247 [Conf]
  10. Oliver Bringmann, Wolfgang Rosenstiel
    Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1999, pp:146-153 [Conf]
  11. Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
    An Architecture for Runtime Evaluation of SoC Reliability. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2006, pp:177-0 [Conf]
  12. Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
    Towards a Framework and a Design Methodology for Autonomic SoC. [Citation Graph (0, 0)][DBLP]
    ICAC, 2005, pp:391-392 [Conf]
  13. Oliver Bringmann, Wolfgang Rosenstiel
    Resource sharing in hierarchical synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:318-325 [Conf]
  14. Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn
    Controller Estimation for FPGA Target Architectures during High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:56-61 [Conf]
  15. Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt
    Synchronization Detection for Multi-Process Hierarchical Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:105-110 [Conf]
  16. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Communication Analysis for Network-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:315-320 [Conf]
  17. Oliver Bringmann, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann
    Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:114-119 [Conf]
  18. Matthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel
    Timing simulation of interconnected AUTOSAR software-components. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:474-479 [Conf]
  19. Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
    Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:338-341 [Conf]
  20. Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel
    A Hybrid Approach for System-Level Design Evaluation. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:165-178 [Conf]
  21. Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel
    Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  22. Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. [Citation Graph (, )][DBLP]


  23. Bottom-up performance analysis considering time slice based software scheduling at system level. [Citation Graph (, )][DBLP]


  24. Probabilistic performance risk analysis at system-level. [Citation Graph (, )][DBLP]


  25. Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation. [Citation Graph (, )][DBLP]


  26. ESL power analysis of embedded processors for temperature and reliability estimations. [Citation Graph (, )][DBLP]


  27. High-performance timing simulation of embedded software. [Citation Graph (, )][DBLP]


  28. White box performance analysis considering static non-preemptive software scheduling. [Citation Graph (, )][DBLP]


  29. Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. [Citation Graph (, )][DBLP]


  30. Simulation-based verification of the MOST NetInterface specification revision 3.0. [Citation Graph (, )][DBLP]


  31. Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures. [Citation Graph (, )][DBLP]


  32. Network-on-Chip Architecture Exploration Framework. [Citation Graph (, )][DBLP]


  33. Device selection for system partitioning. [Citation Graph (, )][DBLP]


  34. Generic Self-Adaptation to Reduce Design Effort for System-on-Chip. [Citation Graph (, )][DBLP]


  35. Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. [Citation Graph (, )][DBLP]


  36. Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). [Citation Graph (, )][DBLP]


  37. Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties. [Citation Graph (, )][DBLP]


  38. SystemC-Based Communication and Performance Analysis. [Citation Graph (, )][DBLP]


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