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Peter Marwedel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Marwedel
    The Design of a Subprocessor with Dynamic Microprogramming with MIMOLA. [Citation Graph (0, 0)][DBLP]
    ARCS, 1980, pp:164-177 [Conf]
  2. Rainer Leupers, Anupam Basu, Peter Marwedel
    Optimized Array Index Computation in DSP Programs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:87-92 [Conf]
  3. Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel
    Optimized address assignment for DSPs with SIMD memory accesses. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:415-420 [Conf]
  4. Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers
    Compiler based exploration of DSP energy savings by SIMD operations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:838-841 [Conf]
  5. Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, Urs Helmig
    Fast, predictable and low energy memory references through architecture-aware compilation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:4-11 [Conf]
  6. Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel
    Scratchpad memory: design alternative for cache on-chip memory in embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:73-78 [Conf]
  7. Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser
    What will system level design be when it grows up? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:123- [Conf]
  8. Peter Marwedel, Catherine H. Gebotys
    Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:72- [Conf]
  9. Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist
    Embedded systems education: how to teach the required skills? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:254-255 [Conf]
  10. Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan
    Evaluating register file size in ASIP design. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:109-114 [Conf]
  11. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Dynamic overlay of scratchpad memory for energy minimization. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:104-109 [Conf]
  12. M. Balakrishnan, Peter Marwedel
    Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:68-74 [Conf]
  13. Ulrich Bieker, Peter Marwedel
    Retargetable Self-Test Program Generation Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:605-611 [Conf]
  14. Peter Marwedel
    A new synthesis for the MIMOLA software system. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:271-277 [Conf]
  15. Peter Marwedel
    Code Generation for Core Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:232-237 [Conf]
  16. Lothar Nowak, Peter Marwedel
    Verification of Hardware Descriptions by Retargetable Code Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:441-447 [Conf]
  17. Peter Marwedel
    Code generation for embedded processors: an introduction. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:14-31 [Conf]
  18. Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, Urs Helmig
    Fast, predictable and low energy memory references through architecture-aware compilation. [Citation Graph (0, 0)][DBLP]
    Design of Systems with Predictable Behaviour, 2004, pp:- [Conf]
  19. Anupam Basu, Rainer Leupers, Peter Marwedel
    Register-Constrained Address Computation in DSP Programs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:929-930 [Conf]
  20. Heiko Falk, Peter Marwedel
    Control Flow Driven Splitting of Loop Nests at the Source Code Level . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10410-10415 [Conf]
  21. Markus Lorenz, Peter Marwedel
    Phase Coupled Code Generation for DSPs Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1270-1275 [Conf]
  22. R. Niemann, Peter Marwedel
    Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:912-913 [Conf]
  23. Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter Marwedel
    Assigning Program and Data Objects to Scratchpad for Energy Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:409-417 [Conf]
  24. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Cache-Aware Scratchpad Allocation Algorithm. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1264-1269 [Conf]
  25. Lars Wehmeyer, Peter Marwedel
    nfluence of Memory Hierarchies on Predictability for Time Constrained Embedded Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:600-605 [Conf]
  26. Peter Marwedel
    Embedded Software: How To Make It Efficient? [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:201-209 [Conf]
  27. Manish Verma, Klaus Petzold, Lars Wehmeyer, Heiko Falk, Peter Marwedel
    Scratchpad Sharing Strategies for Multiprocess Embedded Systems: A First Approach. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:115-120 [Conf]
  28. Peter Marwedel
    The Integrated Design of Computer Systems with Mimola. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1982, pp:45-57 [Conf]
  29. Lothar Nowak, Peter Marwedel
    Ein retargierbarer Mikrocode-Compiler und seine Anwendung in Entwurfsverifikation und Architekturbewertung. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:233-245 [Conf]
  30. Manish Verma, Peter Marwedel
    Memory Optimization Techniques for Low-Power Embedded Processors. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:445- [Conf]
  31. Rainer Leupers, Peter Marwedel
    Algorithms for address assignment in DSP code generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:109-112 [Conf]
  32. Rainer Leupers, Peter Marwedel
    Function inlining under code size constraints for embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:253-256 [Conf]
  33. Peter Marwedel
    Tree-based mapping of algorithms to predefined structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:586-593 [Conf]
  34. Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis
    Low-Energy DSP Code Generation Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:431-437 [Conf]
  35. Peter Marwedel
    Implementations of IF-statements in the TODOS microarchitecture synthesis system. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:249-262 [Conf]
  36. Rainer Leupers, Wolfgang Schenk, Peter Marwedel
    Microcode Generation for Flexible Parallel Target Architectures. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:247-256 [Conf]
  37. M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke
    Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:213-218 [Conf]
  38. Birger Landwehr, Peter Marwedel
    A New Optimization Technique for Improving Resource Exploitation and Critical Path Minimization. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:65-0 [Conf]
  39. Rainer Leupers, Peter Marwedel
    Time-constrained code compaction for DSPs. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:54-59 [Conf]
  40. Peter Marwedel, Birgit Sirocic
    Overcoming The Limitations of Traditional Media For Teaching Modern Processor Desing. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:102-103 [Conf]
  41. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:41-56 [Conf]
  42. Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini
    Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations . [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:279-288 [Conf]
  43. Anupam Basu, Rainer Leupers, Peter Marwedel
    Array Index Allocation under Register Constraints in DSP Programs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:330-335 [Conf]
  44. Anupam Basu, Raj S. Mitra, Peter Marwedel
    Interface Synthesis for Embedded Applications in a Co Design Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:85-90 [Conf]
  45. Rainer Leupers, Peter Marwedel
    Instruction-Set Modeling for ASIP Code Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:77-80 [Conf]
  46. J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
    Hardware-Software Co-Design for Test: It's the Last Straw! [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:506-507 [Conf]
  47. Lars Wehmeyer, Urs Helmig, Peter Marwedel
    Compiler-optimized usage of partitioned memories. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:114-120 [Conf]
  48. Peter Marwedel
    Guest Editor's Introduction: Processor-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:5-6 [Journal]
  49. Peter Marwedel, Carlos A. López-Barrio
    Guest Editor's Introduction: Design, Design Automation, and Test in Europe. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:14-15 [Journal]
  50. Peter Marwedel, Wolfgang Rosenstiel
    Synthese von Register-Transfer-Strukturen aus Verhaltensbeschriebungen. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1992, v:15, n:1, pp:5-22 [Journal]
  51. Peter Marwedel
    Eingebettete Systeme. [Citation Graph (0, 0)][DBLP]
    LOG IN, 2000, v:20, n:6, pp:16-0 [Journal]
  52. Peter Marwedel
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1281-1282 [Journal]
  53. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2035-2051 [Journal]
  54. Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan
    Analysis of the influence of register file size on energyconsumption, code size, and execution time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1329-1337 [Journal]
  55. Peter Marwedel
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:749-751 [Journal]
  56. Manish Verma, Peter Marwedel
    Overlay techniques for scratchpad memories in low power embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:802-815 [Journal]
  57. Lars Wehmeyer, Peter Marwedel
    Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  58. Rainer Leupers, Peter Marwedel
    Time-constrained code compaction for DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:112-122 [Journal]

  59. Superblock-Based Source Code Optimizations for WCET Reduction. [Citation Graph (, )][DBLP]


  60. A Fast and Precise Static Loop Analysis Based on Abstract Interpretation, Program Slicing and Polytope Models. [Citation Graph (, )][DBLP]


  61. Influence of procedure cloning on WCET prediction. [Citation Graph (, )][DBLP]


  62. Retargetable generation of code selectors from HDL processor models. [Citation Graph (, )][DBLP]


  63. WCET-driven Cache-based Procedure Positioning Optimizations. [Citation Graph (, )][DBLP]


  64. Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization. [Citation Graph (, )][DBLP]


  65. OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming. [Citation Graph (, )][DBLP]


  66. Instruction set extraction from programmable structures. [Citation Graph (, )][DBLP]


  67. Matching system and component behaviour in MIMOLA synthesis tools. [Citation Graph (, )][DBLP]


  68. Plädoyer für eine ganzheitliche Betrachtung des Zusammenhangs zwischen Informationstechnologie und CO2-Produktion. [Citation Graph (, )][DBLP]


  69. Versatile system-level memory-aware platform description approach for embedded MPSoCs. [Citation Graph (, )][DBLP]


  70. WCET-driven, code-size critical procedure cloning. [Citation Graph (, )][DBLP]


  71. Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications. [Citation Graph (, )][DBLP]


  72. WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems. [Citation Graph (, )][DBLP]


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