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Kil-Whan Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Woo-Chan Park, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Kyung-Su Kim, Won-Jong Lee, Tack-Don Han, Sung-Bong Yang
    A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:160-175 [Conf]
  2. Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
    A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:173-0 [Conf]
  3. Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, Shin-Dug Kim
    A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure. [Citation Graph (0, 0)][DBLP]
    LCTES, 2000, pp:162-177 [Conf]
  4. Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim
    A Dual Data Cache System to Reflect the Principle of Locality Effectively. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  5. Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
    An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1501-1508 [Journal]
  6. Kil-Whan Lee, Woo-Chan Park, Il-San Kim, Tack-Don Han
    A pixel cache architecture with selective placement scheme based on z-test result. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:1, pp:41-46 [Journal]
  7. Woo-Chan Park, Cheong-Ghil Kim, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Tack-Don Han
    A consistency-free memory architecture for sort-last parallel rendering processors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:272-284 [Journal]

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